0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree file for Marvell Armada 388 evaluation board
0004 * (DB-88F6820)
0005 *
0006 * Copyright (C) 2014 Marvell
0007 *
0008 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0009 */
0010
0011 /dts-v1/;
0012 #include "armada-388.dtsi"
0013
0014 / {
0015 model = "Marvell Armada 385 Development Board";
0016 compatible = "marvell,a385-db", "marvell,armada388",
0017 "marvell,armada385", "marvell,armada380";
0018
0019 chosen {
0020 stdout-path = "serial0:115200n8";
0021 };
0022
0023 memory {
0024 device_type = "memory";
0025 reg = <0x00000000 0x10000000>; /* 256 MB */
0026 };
0027
0028 soc {
0029 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
0030 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
0031 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
0032 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
0033 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
0034
0035 internal-regs {
0036 i2c@11000 {
0037 status = "okay";
0038 clock-frequency = <100000>;
0039 };
0040
0041 i2c@11100 {
0042 status = "okay";
0043 clock-frequency = <100000>;
0044 };
0045
0046 serial@12000 {
0047 status = "okay";
0048 };
0049
0050 ethernet@30000 {
0051 status = "okay";
0052 phy = <&phy1>;
0053 phy-mode = "rgmii-id";
0054 buffer-manager = <&bm>;
0055 bm,pool-long = <2>;
0056 bm,pool-short = <3>;
0057 };
0058
0059 usb@58000 {
0060 status = "ok";
0061 };
0062
0063 ethernet@70000 {
0064 status = "okay";
0065 phy = <&phy0>;
0066 phy-mode = "rgmii-id";
0067 buffer-manager = <&bm>;
0068 bm,pool-long = <0>;
0069 bm,pool-short = <1>;
0070 };
0071
0072 mdio@72004 {
0073 phy0: ethernet-phy@0 {
0074 reg = <0>;
0075 };
0076
0077 phy1: ethernet-phy@1 {
0078 reg = <1>;
0079 };
0080 };
0081
0082 sata@a8000 {
0083 status = "okay";
0084 };
0085
0086 sata@e0000 {
0087 status = "okay";
0088 };
0089
0090 bm@c8000 {
0091 status = "okay";
0092 };
0093
0094 sdhci@d8000 {
0095 broken-cd;
0096 wp-inverted;
0097 bus-width = <8>;
0098 status = "okay";
0099 no-1-8-v;
0100 };
0101
0102 usb3@f0000 {
0103 status = "okay";
0104 };
0105
0106 usb3@f8000 {
0107 status = "okay";
0108 };
0109 };
0110
0111 bm-bppi {
0112 status = "okay";
0113 };
0114
0115 pcie {
0116 status = "okay";
0117 /*
0118 * The two PCIe units are accessible through
0119 * standard PCIe slots on the board.
0120 */
0121 pcie@1,0 {
0122 /* Port 0, Lane 0 */
0123 status = "okay";
0124 };
0125 pcie@2,0 {
0126 /* Port 1, Lane 0 */
0127 status = "okay";
0128 };
0129 };
0130 };
0131 };
0132
0133 &spi0 {
0134 status = "okay";
0135
0136 flash@0 {
0137 #address-cells = <1>;
0138 #size-cells = <1>;
0139 compatible = "w25q32", "jedec,spi-nor";
0140 reg = <0>; /* Chip select 0 */
0141 spi-max-frequency = <108000000>;
0142 };
0143 };
0144
0145 &nand_controller {
0146 status = "okay";
0147
0148 nand@0 {
0149 reg = <0>;
0150 label = "pxa3xx_nand-0";
0151 nand-rb = <0>;
0152 marvell,nand-keep-config;
0153 nand-on-flash-bbt;
0154 nand-ecc-strength = <4>;
0155 nand-ecc-step-size = <512>;
0156
0157 partitions {
0158 compatible = "fixed-partitions";
0159 #address-cells = <1>;
0160 #size-cells = <1>;
0161
0162 partition@0 {
0163 label = "U-Boot";
0164 reg = <0 0x800000>;
0165 };
0166 partition@800000 {
0167 label = "Linux";
0168 reg = <0x800000 0x800000>;
0169 };
0170 partition@1000000 {
0171 label = "Filesystem";
0172 reg = <0x1000000 0x3f000000>;
0173 };
0174 };
0175 };
0176 };
