0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828)
0004 *
0005 * Copyright (C) 2015 Russell King
0006 */
0007
0008 /dts-v1/;
0009 #include "armada-388-clearfog.dtsi"
0010
0011 / {
0012 model = "SolidRun Clearfog Base A1";
0013 compatible = "solidrun,clearfog-base-a1",
0014 "solidrun,clearfog-a1", "marvell,armada388",
0015 "marvell,armada385", "marvell,armada380";
0016
0017 gpio-keys {
0018 compatible = "gpio-keys";
0019 pinctrl-0 = <&rear_button_pins>;
0020 pinctrl-names = "default";
0021
0022 button-0 {
0023 /* The rear SW3 button */
0024 label = "Rear Button";
0025 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
0026 linux,can-disable;
0027 linux,code = <BTN_0>;
0028 };
0029 };
0030 };
0031
0032 ð1 {
0033 phy = <&phy1>;
0034 };
0035
0036 &gpio0 {
0037 phy1_reset {
0038 gpio-hog;
0039 gpios = <19 GPIO_ACTIVE_LOW>;
0040 output-low;
0041 line-name = "phy1-reset";
0042 };
0043 };
0044
0045 &mdio {
0046 pinctrl-0 = <&mdio_pins µsom_phy_clk_pins &clearfog_phy_pins>;
0047 phy1: ethernet-phy@1 {
0048 /*
0049 * Annoyingly, the marvell phy driver configures the LED
0050 * register, rather than preserving reset-loaded setting.
0051 * We undo that rubbish here.
0052 */
0053 marvell,reg-init = <3 16 0 0x101e>;
0054 reg = <1>;
0055 };
0056 };
0057
0058 &pinctrl {
0059 /* phy1 reset */
0060 clearfog_phy_pins: clearfog-phy-pins {
0061 marvell,pins = "mpp19";
0062 marvell,function = "gpio";
0063 };
0064 rear_button_pins: rear-button-pins {
0065 marvell,pins = "mpp44";
0066 marvell,function = "gpio";
0067 };
0068 };