0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Marvell Armada 385 SoC.
0004 *
0005 * Copyright (C) 2014 Marvell
0006 *
0007 * Lior Amsalem <alior@marvell.com>
0008 * Gregory CLEMENT <gregory.clement@free-electrons.com>
0009 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0010 */
0011
0012 #include "armada-38x.dtsi"
0013
0014 / {
0015 model = "Marvell Armada 385 family SoC";
0016 compatible = "marvell,armada385", "marvell,armada380";
0017
0018 cpus {
0019 #address-cells = <1>;
0020 #size-cells = <0>;
0021 enable-method = "marvell,armada-380-smp";
0022
0023 cpu@0 {
0024 device_type = "cpu";
0025 compatible = "arm,cortex-a9";
0026 reg = <0>;
0027 };
0028 cpu@1 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a9";
0031 reg = <1>;
0032 };
0033 };
0034
0035 soc {
0036 pciec: pcie {
0037 compatible = "marvell,armada-370-pcie";
0038 status = "disabled";
0039 device_type = "pci";
0040
0041 #address-cells = <3>;
0042 #size-cells = <2>;
0043
0044 msi-parent = <&mpic>;
0045 bus-range = <0x00 0xff>;
0046
0047 ranges =
0048 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
0049 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0050 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
0051 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
0052 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
0053 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
0054 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
0055 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
0056 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
0057 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
0058 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
0059 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
0060
0061 /*
0062 * This port can be either x4 or x1. When
0063 * configured in x4 by the bootloader, then
0064 * pcie@4,0 is not available.
0065 */
0066 pcie1: pcie@1,0 {
0067 device_type = "pci";
0068 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
0069 reg = <0x0800 0 0 0 0>;
0070 #address-cells = <3>;
0071 #size-cells = <2>;
0072 interrupt-names = "intx";
0073 interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0074 #interrupt-cells = <1>;
0075 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0076 0x81000000 0 0 0x81000000 0x1 0 1 0>;
0077 bus-range = <0x00 0xff>;
0078 interrupt-map-mask = <0 0 0 7>;
0079 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
0080 <0 0 0 2 &pcie1_intc 1>,
0081 <0 0 0 3 &pcie1_intc 2>,
0082 <0 0 0 4 &pcie1_intc 3>;
0083 marvell,pcie-port = <0>;
0084 marvell,pcie-lane = <0>;
0085 clocks = <&gateclk 8>;
0086 status = "disabled";
0087 pcie1_intc: interrupt-controller {
0088 interrupt-controller;
0089 #interrupt-cells = <1>;
0090 };
0091 };
0092
0093 /* x1 port */
0094 pcie2: pcie@2,0 {
0095 device_type = "pci";
0096 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
0097 reg = <0x1000 0 0 0 0>;
0098 #address-cells = <3>;
0099 #size-cells = <2>;
0100 interrupt-names = "intx";
0101 interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0102 #interrupt-cells = <1>;
0103 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0104 0x81000000 0 0 0x81000000 0x2 0 1 0>;
0105 bus-range = <0x00 0xff>;
0106 interrupt-map-mask = <0 0 0 7>;
0107 interrupt-map = <0 0 0 1 &pcie2_intc 0>,
0108 <0 0 0 2 &pcie2_intc 1>,
0109 <0 0 0 3 &pcie2_intc 2>,
0110 <0 0 0 4 &pcie2_intc 3>;
0111 marvell,pcie-port = <1>;
0112 marvell,pcie-lane = <0>;
0113 clocks = <&gateclk 5>;
0114 status = "disabled";
0115 pcie2_intc: interrupt-controller {
0116 interrupt-controller;
0117 #interrupt-cells = <1>;
0118 };
0119 };
0120
0121 /* x1 port */
0122 pcie3: pcie@3,0 {
0123 device_type = "pci";
0124 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
0125 reg = <0x1800 0 0 0 0>;
0126 #address-cells = <3>;
0127 #size-cells = <2>;
0128 interrupt-names = "intx";
0129 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0130 #interrupt-cells = <1>;
0131 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0132 0x81000000 0 0 0x81000000 0x3 0 1 0>;
0133 bus-range = <0x00 0xff>;
0134 interrupt-map-mask = <0 0 0 7>;
0135 interrupt-map = <0 0 0 1 &pcie3_intc 0>,
0136 <0 0 0 2 &pcie3_intc 1>,
0137 <0 0 0 3 &pcie3_intc 2>,
0138 <0 0 0 4 &pcie3_intc 3>;
0139 marvell,pcie-port = <2>;
0140 marvell,pcie-lane = <0>;
0141 clocks = <&gateclk 6>;
0142 status = "disabled";
0143 pcie3_intc: interrupt-controller {
0144 interrupt-controller;
0145 #interrupt-cells = <1>;
0146 };
0147 };
0148
0149 /*
0150 * x1 port only available when pcie@1,0 is
0151 * configured as a x1 port
0152 */
0153 pcie4: pcie@4,0 {
0154 device_type = "pci";
0155 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
0156 reg = <0x2000 0 0 0 0>;
0157 #address-cells = <3>;
0158 #size-cells = <2>;
0159 interrupt-names = "intx";
0160 interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0161 #interrupt-cells = <1>;
0162 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0163 0x81000000 0 0 0x81000000 0x4 0 1 0>;
0164 bus-range = <0x00 0xff>;
0165 interrupt-map-mask = <0 0 0 7>;
0166 interrupt-map = <0 0 0 1 &pcie4_intc 0>,
0167 <0 0 0 2 &pcie4_intc 1>,
0168 <0 0 0 3 &pcie4_intc 2>,
0169 <0 0 0 4 &pcie4_intc 3>;
0170 marvell,pcie-port = <3>;
0171 marvell,pcie-lane = <0>;
0172 clocks = <&gateclk 7>;
0173 status = "disabled";
0174 pcie4_intc: interrupt-controller {
0175 interrupt-controller;
0176 #interrupt-cells = <1>;
0177 };
0178 };
0179 };
0180 };
0181 };
0182
0183 &pinctrl {
0184 compatible = "marvell,mv88f6820-pinctrl";
0185 };
