0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Device Tree file for the Turris Omnia
0004 *
0005 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
0006 * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
0007 *
0008 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
0009 */
0010
0011 /dts-v1/;
0012
0013 #include <dt-bindings/gpio/gpio.h>
0014 #include <dt-bindings/input/input.h>
0015 #include <dt-bindings/leds/common.h>
0016 #include "armada-385.dtsi"
0017
0018 / {
0019 model = "Turris Omnia";
0020 compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
0021
0022 chosen {
0023 stdout-path = &uart0;
0024 };
0025
0026 memory {
0027 device_type = "memory";
0028 reg = <0x00000000 0x40000000>; /* 1024 MB */
0029 };
0030
0031 soc {
0032 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
0033 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
0034 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
0035 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
0036 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
0037
0038 internal-regs {
0039
0040 /* USB part of the PCIe2/USB 2.0 port */
0041 usb@58000 {
0042 status = "okay";
0043 };
0044
0045 sata@a8000 {
0046 status = "okay";
0047 };
0048
0049 sdhci@d8000 {
0050 pinctrl-names = "default";
0051 pinctrl-0 = <&sdhci_pins>;
0052 status = "okay";
0053
0054 bus-width = <8>;
0055 no-1-8-v;
0056 non-removable;
0057 };
0058
0059 usb3@f0000 {
0060 status = "okay";
0061 };
0062
0063 usb3@f8000 {
0064 status = "okay";
0065 };
0066 };
0067
0068 pcie {
0069 status = "okay";
0070
0071 pcie@1,0 {
0072 /* Port 0, Lane 0 */
0073 status = "okay";
0074 slot-power-limit-milliwatt = <10000>;
0075 };
0076
0077 pcie@2,0 {
0078 /* Port 1, Lane 0 */
0079 status = "okay";
0080 slot-power-limit-milliwatt = <10000>;
0081 };
0082
0083 pcie@3,0 {
0084 /* Port 2, Lane 0 */
0085 status = "okay";
0086 slot-power-limit-milliwatt = <10000>;
0087 };
0088 };
0089 };
0090
0091 sfp: sfp {
0092 compatible = "sff,sfp";
0093 i2c-bus = <&sfp_i2c>;
0094 tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
0095 tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
0096 rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
0097 los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
0098 mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
0099 maximum-power-milliwatt = <3000>;
0100
0101 /*
0102 * For now this has to be enabled at boot time by U-Boot when
0103 * a SFP module is present. Read more in the comment in the
0104 * eth2 node below.
0105 */
0106 status = "disabled";
0107 };
0108 };
0109
0110 &bm {
0111 status = "okay";
0112 };
0113
0114 &bm_bppi {
0115 status = "okay";
0116 };
0117
0118 /* Connected to 88E6176 switch, port 6 */
0119 ð0 {
0120 pinctrl-names = "default";
0121 pinctrl-0 = <&ge0_rgmii_pins>;
0122 status = "okay";
0123 phy-mode = "rgmii";
0124 buffer-manager = <&bm>;
0125 bm,pool-long = <0>;
0126 bm,pool-short = <3>;
0127
0128 fixed-link {
0129 speed = <1000>;
0130 full-duplex;
0131 };
0132 };
0133
0134 /* Connected to 88E6176 switch, port 5 */
0135 ð1 {
0136 pinctrl-names = "default";
0137 pinctrl-0 = <&ge1_rgmii_pins>;
0138 status = "okay";
0139 phy-mode = "rgmii";
0140 buffer-manager = <&bm>;
0141 bm,pool-long = <1>;
0142 bm,pool-short = <3>;
0143
0144 fixed-link {
0145 speed = <1000>;
0146 full-duplex;
0147 };
0148 };
0149
0150 /* WAN port */
0151 ð2 {
0152 /*
0153 * eth2 is connected via a multiplexor to both the SFP cage and to
0154 * ethernet-phy@1. The multiplexor switches the signal to SFP cage when
0155 * a SFP module is present, as determined by the mode-def0 GPIO.
0156 *
0157 * Until kernel supports this configuration properly, in case SFP module
0158 * is present, U-Boot has to enable the sfp node above, remove phy
0159 * handle and add managed = "in-band-status" property.
0160 */
0161 status = "okay";
0162 phy-mode = "sgmii";
0163 phy-handle = <&phy1>;
0164 phys = <&comphy5 2>;
0165 sfp = <&sfp>;
0166 buffer-manager = <&bm>;
0167 bm,pool-long = <2>;
0168 bm,pool-short = <3>;
0169 };
0170
0171 &i2c0 {
0172 pinctrl-names = "default";
0173 pinctrl-0 = <&i2c0_pins>;
0174 status = "okay";
0175
0176 i2cmux@70 {
0177 compatible = "nxp,pca9547";
0178 #address-cells = <1>;
0179 #size-cells = <0>;
0180 reg = <0x70>;
0181
0182 i2c@0 {
0183 #address-cells = <1>;
0184 #size-cells = <0>;
0185 reg = <0>;
0186
0187 /* STM32F0 command interface at address 0x2a */
0188
0189 led-controller@2b {
0190 compatible = "cznic,turris-omnia-leds";
0191 reg = <0x2b>;
0192 #address-cells = <1>;
0193 #size-cells = <0>;
0194 status = "okay";
0195
0196 /*
0197 * LEDs are controlled by MCU (STM32F0) at
0198 * address 0x2b.
0199 *
0200 * LED functions are not stable yet:
0201 * - there are 3 LEDs connected via MCU to PCIe
0202 * ports. One of these ports supports mSATA.
0203 * There is no mSATA nor PCIe function.
0204 * For now we use LED_FUNCTION_WLAN, since
0205 * in most cases users have wifi cards in
0206 * these slots
0207 * - there are 2 LEDs dedicated for user: A and
0208 * B. Again there is no such function defined.
0209 * For now we use LED_FUNCTION_INDICATOR
0210 */
0211
0212 multi-led@0 {
0213 reg = <0x0>;
0214 color = <LED_COLOR_ID_RGB>;
0215 function = LED_FUNCTION_INDICATOR;
0216 function-enumerator = <2>;
0217 };
0218
0219 multi-led@1 {
0220 reg = <0x1>;
0221 color = <LED_COLOR_ID_RGB>;
0222 function = LED_FUNCTION_INDICATOR;
0223 function-enumerator = <1>;
0224 };
0225
0226 multi-led@2 {
0227 reg = <0x2>;
0228 color = <LED_COLOR_ID_RGB>;
0229 function = LED_FUNCTION_WLAN;
0230 function-enumerator = <3>;
0231 };
0232
0233 multi-led@3 {
0234 reg = <0x3>;
0235 color = <LED_COLOR_ID_RGB>;
0236 function = LED_FUNCTION_WLAN;
0237 function-enumerator = <2>;
0238 };
0239
0240 multi-led@4 {
0241 reg = <0x4>;
0242 color = <LED_COLOR_ID_RGB>;
0243 function = LED_FUNCTION_WLAN;
0244 function-enumerator = <1>;
0245 };
0246
0247 multi-led@5 {
0248 reg = <0x5>;
0249 color = <LED_COLOR_ID_RGB>;
0250 function = LED_FUNCTION_WAN;
0251 };
0252
0253 multi-led@6 {
0254 reg = <0x6>;
0255 color = <LED_COLOR_ID_RGB>;
0256 function = LED_FUNCTION_LAN;
0257 function-enumerator = <4>;
0258 };
0259
0260 multi-led@7 {
0261 reg = <0x7>;
0262 color = <LED_COLOR_ID_RGB>;
0263 function = LED_FUNCTION_LAN;
0264 function-enumerator = <3>;
0265 };
0266
0267 multi-led@8 {
0268 reg = <0x8>;
0269 color = <LED_COLOR_ID_RGB>;
0270 function = LED_FUNCTION_LAN;
0271 function-enumerator = <2>;
0272 };
0273
0274 multi-led@9 {
0275 reg = <0x9>;
0276 color = <LED_COLOR_ID_RGB>;
0277 function = LED_FUNCTION_LAN;
0278 function-enumerator = <1>;
0279 };
0280
0281 multi-led@a {
0282 reg = <0xa>;
0283 color = <LED_COLOR_ID_RGB>;
0284 function = LED_FUNCTION_LAN;
0285 function-enumerator = <0>;
0286 };
0287
0288 multi-led@b {
0289 reg = <0xb>;
0290 color = <LED_COLOR_ID_RGB>;
0291 function = LED_FUNCTION_POWER;
0292 };
0293 };
0294
0295 eeprom@54 {
0296 compatible = "atmel,24c64";
0297 reg = <0x54>;
0298
0299 /* The EEPROM contains data for bootloader.
0300 * Contents:
0301 * struct omnia_eeprom {
0302 * u32 magic; (=0x0341a034 in LE)
0303 * u32 ramsize; (in GiB)
0304 * char regdomain[4];
0305 * u32 crc32;
0306 * };
0307 */
0308 };
0309 };
0310
0311 i2c@1 {
0312 #address-cells = <1>;
0313 #size-cells = <0>;
0314 reg = <1>;
0315
0316 /* routed to PCIe0/mSATA connector (CN7A) */
0317 };
0318
0319 i2c@2 {
0320 #address-cells = <1>;
0321 #size-cells = <0>;
0322 reg = <2>;
0323
0324 /* routed to PCIe1/USB2 connector (CN61A) */
0325 };
0326
0327 i2c@3 {
0328 #address-cells = <1>;
0329 #size-cells = <0>;
0330 reg = <3>;
0331
0332 /* routed to PCIe2 connector (CN62A) */
0333 };
0334
0335 sfp_i2c: i2c@4 {
0336 #address-cells = <1>;
0337 #size-cells = <0>;
0338 reg = <4>;
0339
0340 /* routed to SFP+ */
0341 };
0342
0343 i2c@5 {
0344 #address-cells = <1>;
0345 #size-cells = <0>;
0346 reg = <5>;
0347
0348 /* ATSHA204A-MAHDA-T crypto module */
0349 crypto@64 {
0350 compatible = "atmel,atsha204a";
0351 reg = <0x64>;
0352 };
0353 };
0354
0355 i2c@6 {
0356 #address-cells = <1>;
0357 #size-cells = <0>;
0358 reg = <6>;
0359
0360 /* exposed on pin header */
0361 };
0362
0363 i2c@7 {
0364 #address-cells = <1>;
0365 #size-cells = <0>;
0366 reg = <7>;
0367
0368 pcawan: gpio@71 {
0369 /*
0370 * GPIO expander for SFP+ signals and
0371 * and phy irq
0372 */
0373 compatible = "nxp,pca9538";
0374 reg = <0x71>;
0375
0376 pinctrl-names = "default";
0377 pinctrl-0 = <&pcawan_pins>;
0378
0379 interrupt-parent = <&gpio1>;
0380 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
0381
0382 gpio-controller;
0383 #gpio-cells = <2>;
0384 };
0385 };
0386 };
0387 };
0388
0389 &mdio {
0390 pinctrl-names = "default";
0391 pinctrl-0 = <&mdio_pins>;
0392 status = "okay";
0393
0394 phy1: ethernet-phy@1 {
0395 compatible = "ethernet-phy-ieee802.3-c22";
0396 reg = <1>;
0397 marvell,reg-init = <3 18 0 0x4985>,
0398 <3 16 0xfff0 0x0001>;
0399
0400 /* irq is connected to &pcawan pin 7 */
0401 };
0402
0403 /* Switch MV88E6176 at address 0x10 */
0404 switch@10 {
0405 pinctrl-names = "default";
0406 pinctrl-0 = <&swint_pins>;
0407 compatible = "marvell,mv88e6085";
0408 #address-cells = <1>;
0409 #size-cells = <0>;
0410
0411 dsa,member = <0 0>;
0412 reg = <0x10>;
0413
0414 interrupt-parent = <&gpio1>;
0415 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
0416
0417 ports {
0418 #address-cells = <1>;
0419 #size-cells = <0>;
0420
0421 ports@0 {
0422 reg = <0>;
0423 label = "lan0";
0424 };
0425
0426 ports@1 {
0427 reg = <1>;
0428 label = "lan1";
0429 };
0430
0431 ports@2 {
0432 reg = <2>;
0433 label = "lan2";
0434 };
0435
0436 ports@3 {
0437 reg = <3>;
0438 label = "lan3";
0439 };
0440
0441 ports@4 {
0442 reg = <4>;
0443 label = "lan4";
0444 };
0445
0446 ports@5 {
0447 reg = <5>;
0448 label = "cpu";
0449 ethernet = <ð1>;
0450 phy-mode = "rgmii-id";
0451
0452 fixed-link {
0453 speed = <1000>;
0454 full-duplex;
0455 };
0456 };
0457
0458 /* port 6 is connected to eth0 */
0459 };
0460 };
0461 };
0462
0463 &pinctrl {
0464 pcawan_pins: pcawan-pins {
0465 marvell,pins = "mpp46";
0466 marvell,function = "gpio";
0467 };
0468
0469 swint_pins: swint-pins {
0470 marvell,pins = "mpp45";
0471 marvell,function = "gpio";
0472 };
0473
0474 spi0cs0_pins: spi0cs0-pins {
0475 marvell,pins = "mpp25";
0476 marvell,function = "spi0";
0477 };
0478
0479 spi0cs1_pins: spi0cs1-pins {
0480 marvell,pins = "mpp26";
0481 marvell,function = "spi0";
0482 };
0483 };
0484
0485 &spi0 {
0486 pinctrl-names = "default";
0487 pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
0488 status = "okay";
0489
0490 flash@0 {
0491 compatible = "spansion,s25fl164k", "jedec,spi-nor";
0492 #address-cells = <1>;
0493 #size-cells = <1>;
0494 reg = <0>;
0495 spi-max-frequency = <40000000>;
0496
0497 partitions {
0498 compatible = "fixed-partitions";
0499 #address-cells = <1>;
0500 #size-cells = <1>;
0501
0502 partition@0 {
0503 reg = <0x0 0x00100000>;
0504 label = "U-Boot";
0505 };
0506
0507 partition@100000 {
0508 reg = <0x00100000 0x00700000>;
0509 label = "Rescue system";
0510 };
0511 };
0512 };
0513
0514 /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
0515 };
0516
0517 &uart0 {
0518 /* Pin header CN10 */
0519 pinctrl-names = "default";
0520 pinctrl-0 = <&uart0_pins>;
0521 status = "okay";
0522 };
0523
0524 &uart1 {
0525 /* Pin header CN11 */
0526 pinctrl-names = "default";
0527 pinctrl-0 = <&uart1_pins>;
0528 status = "okay";
0529 };
