0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Device Tree file for Marvell Armada 385 Access Point Development board
0004 * (DB-88F6820-AP)
0005 *
0006 * Copyright (C) 2014 Marvell
0007 *
0008 * Nadav Haklai <nadavh@marvell.com>
0009 */
0010
0011 /dts-v1/;
0012 #include "armada-385.dtsi"
0013
0014 #include <dt-bindings/gpio/gpio.h>
0015
0016 / {
0017 model = "Marvell Armada 385 Access Point Development Board";
0018 compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
0019
0020 chosen {
0021 stdout-path = "serial1:115200n8";
0022 };
0023
0024 memory {
0025 device_type = "memory";
0026 reg = <0x00000000 0x80000000>; /* 2GB */
0027 };
0028
0029 soc {
0030 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
0031 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
0032 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
0033 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
0034 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
0035
0036 internal-regs {
0037 i2c0: i2c@11000 {
0038 pinctrl-names = "default";
0039 pinctrl-0 = <&i2c0_pins>;
0040 status = "okay";
0041
0042 /*
0043 * This bus is wired to two EEPROM
0044 * sockets, one of which holding the
0045 * board ID used by the bootloader.
0046 * Erasing this EEPROM's content will
0047 * brick the board.
0048 * Use this bus with caution.
0049 */
0050 };
0051
0052 mdio@72004 {
0053 pinctrl-names = "default";
0054 pinctrl-0 = <&mdio_pins>;
0055
0056 phy0: ethernet-phy@1 {
0057 reg = <1>;
0058 };
0059
0060 phy1: ethernet-phy@4 {
0061 reg = <4>;
0062 };
0063
0064 phy2: ethernet-phy@6 {
0065 reg = <6>;
0066 };
0067 };
0068
0069 /* UART0 is exposed through the JP8 connector */
0070 uart0: serial@12000 {
0071 pinctrl-names = "default";
0072 pinctrl-0 = <&uart0_pins>;
0073 status = "okay";
0074 };
0075
0076 /*
0077 * UART1 is exposed through a FTDI chip
0078 * wired to the mini-USB connector
0079 */
0080 uart1: serial@12100 {
0081 pinctrl-names = "default";
0082 pinctrl-0 = <&uart1_pins>;
0083 status = "okay";
0084 };
0085
0086 pinctrl@18000 {
0087 xhci0_vbus_pins: xhci0-vbus-pins {
0088 marvell,pins = "mpp44";
0089 marvell,function = "gpio";
0090 };
0091 };
0092
0093 /* CON3 */
0094 ethernet@30000 {
0095 status = "okay";
0096 phy = <&phy2>;
0097 phy-mode = "sgmii";
0098 buffer-manager = <&bm>;
0099 bm,pool-long = <1>;
0100 bm,pool-short = <3>;
0101 };
0102
0103 /* CON2 */
0104 ethernet@34000 {
0105 status = "okay";
0106 phy = <&phy1>;
0107 phy-mode = "sgmii";
0108 buffer-manager = <&bm>;
0109 bm,pool-long = <2>;
0110 bm,pool-short = <3>;
0111 };
0112
0113 usb@58000 {
0114 status = "okay";
0115 };
0116
0117 /* CON4 */
0118 ethernet@70000 {
0119 pinctrl-names = "default";
0120
0121 /*
0122 * The Reference Clock 0 is used to
0123 * provide a clock to the PHY
0124 */
0125 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
0126 status = "okay";
0127 phy = <&phy0>;
0128 phy-mode = "rgmii-id";
0129 buffer-manager = <&bm>;
0130 bm,pool-long = <0>;
0131 bm,pool-short = <3>;
0132 };
0133
0134 bm@c8000 {
0135 status = "okay";
0136 };
0137
0138 usb3@f0000 {
0139 status = "okay";
0140 usb-phy = <&usb3_phy>;
0141 };
0142 };
0143
0144 bm-bppi {
0145 status = "okay";
0146 };
0147
0148 pcie {
0149 status = "okay";
0150
0151 /*
0152 * The three PCIe units are accessible through
0153 * standard mini-PCIe slots on the board.
0154 */
0155 pcie@1,0 {
0156 /* Port 0, Lane 0 */
0157 status = "okay";
0158 };
0159
0160 pcie@2,0 {
0161 /* Port 1, Lane 0 */
0162 status = "okay";
0163 };
0164
0165 pcie@3,0 {
0166 /* Port 2, Lane 0 */
0167 status = "okay";
0168 };
0169 };
0170 };
0171
0172 usb3_phy: usb3_phy {
0173 compatible = "usb-nop-xceiv";
0174 vcc-supply = <®_xhci0_vbus>;
0175 #phy-cells = <0>;
0176 };
0177
0178 reg_xhci0_vbus: xhci0-vbus {
0179 compatible = "regulator-fixed";
0180 pinctrl-names = "default";
0181 pinctrl-0 = <&xhci0_vbus_pins>;
0182 regulator-name = "xhci0-vbus";
0183 regulator-min-microvolt = <5000000>;
0184 regulator-max-microvolt = <5000000>;
0185 enable-active-high;
0186 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
0187 };
0188 };
0189
0190 &spi1 {
0191 pinctrl-names = "default";
0192 pinctrl-0 = <&spi1_pins>;
0193 status = "okay";
0194
0195 flash@0 {
0196 #address-cells = <1>;
0197 #size-cells = <1>;
0198 compatible = "st,m25p128", "jedec,spi-nor";
0199 reg = <0>; /* Chip select 0 */
0200 spi-max-frequency = <54000000>;
0201 };
0202 };
0203
0204 &nand_controller {
0205 status = "okay";
0206
0207 nand@0 {
0208 reg = <0>;
0209 label = "pxa3xx_nand-0";
0210 nand-rb = <0>;
0211 nand-on-flash-bbt;
0212 nand-ecc-strength = <4>;
0213 nand-ecc-step-size = <512>;
0214
0215 partitions {
0216 compatible = "fixed-partitions";
0217 #address-cells = <1>;
0218 #size-cells = <1>;
0219
0220 partition@0 {
0221 label = "U-Boot";
0222 reg = <0x00000000 0x00800000>;
0223 read-only;
0224 };
0225
0226 partition@800000 {
0227 label = "uImage";
0228 reg = <0x00800000 0x00400000>;
0229 read-only;
0230 };
0231
0232 partition@c00000 {
0233 label = "Root";
0234 reg = <0x00c00000 0x3f400000>;
0235 };
0236 };
0237 };
0238 };
