0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Device Tree file for Clearfog GTR machines rev 1.0 (88F6825)
0004 *
0005 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
0006 */
0007
0008 /*
0009 SERDES mapping -
0010 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
0011 1. 6141 switch (2.5Gbps capable)
0012 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
0013 3. USB 3.0 Host
0014 4. mini PCIe CON2 - PCIe2
0015 5. SFP connector, or optionally SGMII Ethernet 1512 PHY
0016
0017 USB 2.0 mapping -
0018 0. USB 2.0 - 0 USB pins header CON12
0019 1. USB 2.0 - 1 mini PCIe CON2
0020 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
0021
0022 Pin mapping -
0023 0,1 - console UART
0024 2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors,
0025 front panel and PSE controller
0026 4,5 - MDC/MDIO
0027 6..17 - RGMII
0028 18 - Topaz switch reset (active low)
0029 19 - 1512 phy reset
0030 20 - 1512 phy reset (eth2, optional)
0031 21,28,37,38,39,40 - SD0
0032 22 - USB 3.0 current limiter enable (active high)
0033 24 - SFP TX fault (input active high)
0034 25 - SFP present (input active low)
0035 26,27 - I2C1 - connected to SFP
0036 29 - Fan PWM
0037 30 - CON4 mini PCIe wifi disable
0038 31 - CON3 mini PCIe wifi disable
0039 32 - Fuse programming power toggle (1.8v)
0040 33 - CON4 mini PCIe reset
0041 34 - CON2 mini PCIe wifi disable
0042 35 - CON3 mini PCIe reset
0043 36 - Rear button (GPIO active low)
0044 41 - CON1 front panel connector
0045 42 - Front LED1, or front panel CON1
0046 43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS
0047 44 - CON2 mini PCIe reset
0048 45 - TPM PIRQ signal, or front panel CON1
0049 46 - SFP TX disable
0050 47 - Control isolation of boot sensitive SAR signals
0051 48 - PSE reset
0052 49 - PSE OSS signal
0053 50 - PSE interrupt
0054 52 - Front LED2, or front panel
0055 53 - Front button
0056 54 - SFP LOS (input active high)
0057 55 - Fan sense
0058 56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM
0059 59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable)
0060 */
0061
0062 /dts-v1/;
0063 #include <dt-bindings/input/input.h>
0064 #include <dt-bindings/gpio/gpio.h>
0065 #include <dt-bindings/leds/common.h>
0066 #include "armada-385.dtsi"
0067
0068 / {
0069 compatible = "marvell,armada385", "marvell,armada380";
0070
0071 aliases {
0072 /* So that mvebu u-boot can update the MAC addresses */
0073 ethernet1 = ð0;
0074 ethernet2 = ð1;
0075 ethernet3 = ð2;
0076 i2c0 = &i2c0;
0077 i2c1 = &i2c1;
0078 };
0079
0080 chosen {
0081 stdout-path = "serial0:115200n8";
0082 };
0083
0084 memory {
0085 device_type = "memory";
0086 reg = <0x00000000 0x10000000>; /* 256 MB */
0087 };
0088
0089 reg_3p3v: regulator-3p3v {
0090 compatible = "regulator-fixed";
0091 regulator-name = "3P3V";
0092 regulator-min-microvolt = <3300000>;
0093 regulator-max-microvolt = <3300000>;
0094 regulator-always-on;
0095 };
0096
0097 reg_5p0v: regulator-5p0v {
0098 compatible = "regulator-fixed";
0099 regulator-name = "5P0V";
0100 regulator-min-microvolt = <5000000>;
0101 regulator-max-microvolt = <5000000>;
0102 regulator-always-on;
0103 };
0104
0105 v_usb3_con: regulator-v-usb3-con {
0106 compatible = "regulator-fixed";
0107 gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
0108 pinctrl-names = "default";
0109 pinctrl-0 = <&cf_gtr_usb3_con_vbus>;
0110 regulator-max-microvolt = <5000000>;
0111 regulator-min-microvolt = <5000000>;
0112 regulator-name = "v_usb3_con";
0113 vin-supply = <®_5p0v>;
0114 regulator-boot-on;
0115 regulator-always-on;
0116 };
0117
0118 soc {
0119 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
0120 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
0121 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
0122 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
0123 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
0124
0125 internal-regs {
0126
0127 rtc@a3800 {
0128 status = "okay";
0129 };
0130
0131 i2c@11000 { /* ROM, temp sensor and front panel */
0132 pinctrl-0 = <&i2c0_pins>;
0133 pinctrl-names = "default";
0134 status = "okay";
0135 };
0136
0137 i2c@11100 { /* SFP (CON5/CON6) */
0138 pinctrl-0 = <&cf_gtr_i2c1_pins>;
0139 pinctrl-names = "default";
0140 status = "okay";
0141 };
0142
0143 pinctrl@18000 {
0144 cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
0145 marvell,pins = "mpp18";
0146 marvell,function = "gpio";
0147 };
0148
0149 cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
0150 marvell,pins = "mpp22";
0151 marvell,function = "gpio";
0152 };
0153
0154 cf_gtr_fan_pwm: cf-gtr-fan-pwm {
0155 marvell,pins = "mpp23";
0156 marvell,function = "gpio";
0157 };
0158
0159 cf_gtr_i2c1_pins: i2c1-pins {
0160 /* SFP */
0161 marvell,pins = "mpp26", "mpp27";
0162 marvell,function = "i2c1";
0163 };
0164
0165 cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
0166 marvell,pins = "mpp21", "mpp28",
0167 "mpp37", "mpp38",
0168 "mpp39", "mpp40";
0169 marvell,function = "sd0";
0170 };
0171
0172 cf_gtr_isolation_pins: cf-gtr-isolation-pins {
0173 marvell,pins = "mpp47";
0174 marvell,function = "gpio";
0175 };
0176
0177 cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
0178 marvell,pins = "mpp48";
0179 marvell,function = "gpio";
0180 };
0181
0182 cf_gtr_spi1_cs_pins: spi1-cs-pins {
0183 marvell,pins = "mpp59";
0184 marvell,function = "spi1";
0185 };
0186
0187 cf_gtr_front_button_pins: cf-gtr-front-button-pins {
0188 marvell,pins = "mpp53";
0189 marvell,function = "gpio";
0190 };
0191
0192 cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
0193 marvell,pins = "mpp36";
0194 marvell,function = "gpio";
0195 };
0196 };
0197
0198 sdhci@d8000 {
0199 bus-width = <4>;
0200 no-1-8-v;
0201 non-removable;
0202 pinctrl-0 = <&cf_gtr_sdhci_pins>;
0203 pinctrl-names = "default";
0204 status = "okay";
0205 vmmc = <®_3p3v>;
0206 wp-inverted;
0207 };
0208
0209 usb@58000 {
0210 status = "okay";
0211 };
0212
0213 usb3@f0000 {
0214 status = "okay";
0215 };
0216
0217 usb3@f8000 {
0218 vbus-supply = <&v_usb3_con>;
0219 status = "okay";
0220 };
0221 };
0222
0223 pcie {
0224 status = "okay";
0225 /*
0226 * The PCIe units are accessible through
0227 * the mini-PCIe connectors on the board.
0228 */
0229 pcie@1,0 {
0230 reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
0231 status = "okay";
0232 };
0233
0234 pcie@2,0 {
0235 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
0236 status = "okay";
0237 };
0238
0239 pcie@3,0 {
0240 reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
0241 status = "okay";
0242 };
0243 };
0244 };
0245
0246 sfp0: sfp {
0247 compatible = "sff,sfp";
0248 i2c-bus = <&i2c1>;
0249 los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
0250 mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
0251 tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
0252 };
0253
0254 gpio-keys {
0255 compatible = "gpio-keys";
0256 pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>;
0257 pinctrl-names = "default";
0258
0259 button-0 {
0260 label = "Rear Button";
0261 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
0262 linux,can-disable;
0263 linux,code = <BTN_0>;
0264 };
0265
0266 button-1 {
0267 label = "Front Button";
0268 gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
0269 linux,can-disable;
0270 linux,code = <BTN_1>;
0271 };
0272 };
0273
0274 gpio-leds {
0275 compatible = "gpio-leds";
0276
0277 led1 {
0278 function = LED_FUNCTION_CPU;
0279 color = <LED_COLOR_ID_GREEN>;
0280 gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
0281 };
0282
0283 led2 {
0284 function = LED_FUNCTION_HEARTBEAT;
0285 color = <LED_COLOR_ID_GREEN>;
0286 gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
0287 };
0288 };
0289 };
0290
0291 &bm {
0292 status = "okay";
0293 };
0294
0295 &bm_bppi {
0296 status = "okay";
0297 };
0298
0299 ð0 {
0300 /* ethernet@70000 */
0301 pinctrl-0 = <&ge0_rgmii_pins>;
0302 pinctrl-names = "default";
0303 phy = <&phy_dedicated>;
0304 phy-mode = "rgmii-id";
0305 buffer-manager = <&bm>;
0306 bm,pool-long = <0>;
0307 bm,pool-short = <1>;
0308 status = "okay";
0309 };
0310
0311 ð1 {
0312 /* ethernet@30000 */
0313 bm,pool-long = <2>;
0314 bm,pool-short = <1>;
0315 buffer-manager = <&bm>;
0316 phys = <&comphy1 1>;
0317 phy-mode = "2500base-x";
0318 status = "okay";
0319
0320 fixed-link {
0321 speed = <2500>;
0322 full-duplex;
0323 };
0324 };
0325
0326 ð2 {
0327 /* ethernet@34000 */
0328 bm,pool-long = <3>;
0329 bm,pool-short = <1>;
0330 buffer-manager = <&bm>;
0331 managed = "in-band-status";
0332 phys = <&comphy5 1>;
0333 phy-mode = "sgmii";
0334 sfp = <&sfp0>;
0335 status = "okay";
0336 };
0337
0338 &mdio {
0339 pinctrl-names = "default";
0340 pinctrl-0 = <&mdio_pins>;
0341 status = "okay";
0342
0343 phy_dedicated: ethernet-phy@0 {
0344 /*
0345 * Annoyingly, the marvell phy driver configures the LED
0346 * register, rather than preserving reset-loaded setting.
0347 * We undo that rubbish here.
0348 */
0349 marvell,reg-init = <3 16 0 0x1017>;
0350 reg = <0>;
0351 };
0352 };
0353
0354 &uart0 {
0355 pinctrl-0 = <&uart0_pins>;
0356 pinctrl-names = "default";
0357 status = "okay";
0358 };
0359
0360 &spi1 {
0361 /*
0362 * CS0: W25Q32 flash
0363 */
0364 pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>;
0365 pinctrl-names = "default";
0366 status = "okay";
0367
0368 flash@0 {
0369 #address-cells = <1>;
0370 #size-cells = <0>;
0371 compatible = "w25q32", "jedec,spi-nor";
0372 reg = <0>; /* Chip select 0 */
0373 spi-max-frequency = <3000000>;
0374 status = "okay";
0375 };
0376 };
0377
0378 &i2c0 {
0379 pinctrl-0 = <&i2c0_pins>;
0380 pinctrl-names = "default";
0381 status = "okay";
0382
0383 /* U26 temperature sensor placed near SoC */
0384 temp1: nct75@4c {
0385 compatible = "lm75";
0386 reg = <0x4c>;
0387 };
0388
0389 /* U27 temperature sensor placed near RTC battery */
0390 temp2: nct75@4d {
0391 compatible = "lm75";
0392 reg = <0x4d>;
0393 };
0394
0395 /* 2Kb eeprom */
0396 eeprom@53 {
0397 compatible = "atmel,24c02";
0398 reg = <0x53>;
0399 };
0400 };
0401
0402 &ahci0 {
0403 status = "okay";
0404 };
0405
0406 &ahci1 {
0407 status = "okay";
0408 };
0409
0410 &gpio0 {
0411 pinctrl-0 = <&cf_gtr_fan_pwm>;
0412 pinctrl-names = "default";
0413
0414 wifi-disable {
0415 gpio-hog;
0416 gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>;
0417 output-low;
0418 line-name = "wifi-disable";
0419 };
0420 };
0421
0422 &gpio1 {
0423 pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
0424 pinctrl-names = "default";
0425
0426 lte-disable {
0427 gpio-hog;
0428 gpios = <2 GPIO_ACTIVE_LOW>;
0429 output-low;
0430 line-name = "lte-disable";
0431 };
0432
0433 /*
0434 * This signal, when asserted, isolates Armada 38x sample at reset pins
0435 * from control of external devices. Should be de-asserted after reset.
0436 */
0437 sar-isolation {
0438 gpio-hog;
0439 gpios = <15 GPIO_ACTIVE_LOW>;
0440 output-low;
0441 line-name = "sar-isolation";
0442 };
0443
0444 poe-reset {
0445 gpio-hog;
0446 gpios = <16 GPIO_ACTIVE_LOW>;
0447 output-low;
0448 line-name = "poe-reset";
0449 };
0450 };
