boot/dts/armada-385-clearfog-gtr-s4.dts

0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002
0003 #include "armada-385-clearfog-gtr.dtsi"
0004
0005 / {
0006         model = "SolidRun Clearfog GTR S4";
0007 };
0008
0009 &sfp0 {
0010         tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
0011 };
0012
0013 &mdio {
0014         switch0: switch0@4 {
0015                 compatible = "marvell,mv88e6085";
0016                 reg = <4>;
0017                 pinctrl-names = "default";
0018                 pinctrl-0 = <&cf_gtr_switch_reset_pins>;
0019                 reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
0020
0021                 ports {
0022                         #address-cells = <1>;
0023                         #size-cells = <0>;
0024
0025                         port@1 {
0026                                 reg = <1>;
0027                                 label = "lan2";
0028                                 phy-handle = <&switch0phy0>;
0029                         };
0030
0031                         port@2 {
0032                                 reg = <2>;
0033                                 label = "lan1";
0034                                 phy-handle = <&switch0phy1>;
0035                         };
0036
0037                         port@3 {
0038                                 reg = <3>;
0039                                 label = "lan4";
0040                                 phy-handle = <&switch0phy2>;
0041                         };
0042
0043                         port@4 {
0044                                 reg = <4>;
0045                                 label = "lan3";
0046                                 phy-handle = <&switch0phy3>;
0047                         };
0048
0049                         port@5 {
0050                                 reg = <5>;
0051                                 label = "cpu";
0052                                 ethernet = <&eth1>;
0053                         };
0054
0055                 };
0056
0057                 mdio {
0058                         #address-cells = <1>;
0059                         #size-cells = <0>;
0060
0061                         switch0phy0: switch0phy0@11 {
0062                                 reg = <0x11>;
0063                         };
0064
0065                         switch0phy1: switch0phy1@12 {
0066                                 reg = <0x12>;
0067                         };
0068
0069                         switch0phy2: switch0phy2@13 {
0070                                 reg = <0x13>;
0071                         };
0072
0073                         switch0phy3: switch0phy3@14 {
0074                                 reg = <0x14>;
0075                         };
0076                 };
0077
0078         };
0079 };