boot/dts/armada-385-clearfog-gtr-l8.dts

0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002
0003 #include "armada-385-clearfog-gtr.dtsi"
0004
0005 / {
0006         model = "SolidRun Clearfog GTR L8";
0007 };
0008
0009 &mdio {
0010         switch0: switch0@4 {
0011                 compatible = "marvell,mv88e6190";
0012                 reg = <4>;
0013                 pinctrl-names = "default";
0014                 pinctrl-0 = <&cf_gtr_switch_reset_pins>;
0015                 reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
0016
0017                 ports {
0018                         #address-cells = <1>;
0019                         #size-cells = <0>;
0020
0021                         port@1 {
0022                                 reg = <1>;
0023                                 label = "lan8";
0024                                 phy-handle = <&switch0phy0>;
0025                         };
0026
0027                         port@2 {
0028                                 reg = <2>;
0029                                 label = "lan7";
0030                                 phy-handle = <&switch0phy1>;
0031                         };
0032
0033                         port@3 {
0034                                 reg = <3>;
0035                                 label = "lan6";
0036                                 phy-handle = <&switch0phy2>;
0037                         };
0038
0039                         port@4 {
0040                                 reg = <4>;
0041                                 label = "lan5";
0042                                 phy-handle = <&switch0phy3>;
0043                         };
0044
0045                         port@5 {
0046                                 reg = <5>;
0047                                 label = "lan4";
0048                                 phy-handle = <&switch0phy4>;
0049                         };
0050
0051                         port@6 {
0052                                 reg = <6>;
0053                                 label = "lan3";
0054                                 phy-handle = <&switch0phy5>;
0055                         };
0056
0057                         port@7 {
0058                                 reg = <7>;
0059                                 label = "lan2";
0060                                 phy-handle = <&switch0phy6>;
0061                         };
0062
0063                         port@8 {
0064                                 reg = <8>;
0065                                 label = "lan1";
0066                                 phy-handle = <&switch0phy7>;
0067                         };
0068
0069                         port@10 {
0070                                 reg = <10>;
0071                                 label = "cpu";
0072                                 ethernet = <&eth1>;
0073                         };
0074
0075                 };
0076
0077                 mdio {
0078                         #address-cells = <1>;
0079                         #size-cells = <0>;
0080
0081                         switch0phy0: switch0phy0@1 {
0082                                 reg = <0x1>;
0083                         };
0084
0085                         switch0phy1: switch0phy1@2 {
0086                                 reg = <0x2>;
0087                         };
0088
0089                         switch0phy2: switch0phy2@3 {
0090                                 reg = <0x3>;
0091                         };
0092
0093                         switch0phy3: switch0phy3@4 {
0094                                 reg = <0x4>;
0095                         };
0096
0097                         switch0phy4: switch0phy4@5 {
0098                                 reg = <0x5>;
0099                         };
0100
0101                         switch0phy5: switch0phy5@6 {
0102                                 reg = <0x6>;
0103                         };
0104
0105                         switch0phy6: switch0phy6@7 {
0106                                 reg = <0x7>;
0107                         };
0108
0109                         switch0phy7: switch0phy7@8 {
0110                                 reg = <0x8>;
0111                         };
0112                 };
0113
0114         };
0115 };