0001 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
0002 /* Copyright (c) 2021, Marcel Ziswiler <marcel@ziswiler.com> */
0003
0004 /dts-v1/;
0005 #include "armada-385.dtsi"
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/input/input.h>
0008
0009 / {
0010 model = "Netgear GS110EMX";
0011 compatible = "netgear,gs110emx", "marvell,armada380";
0012
0013 aliases {
0014 /* So that mvebu u-boot can update the MAC addresses */
0015 ethernet1 = ð0;
0016 };
0017
0018 chosen {
0019 stdout-path = "serial0:115200n8";
0020 };
0021
0022 gpio-keys {
0023 compatible = "gpio-keys";
0024 pinctrl-0 = <&front_button_pins>;
0025 pinctrl-names = "default";
0026
0027 key-factory-default {
0028 label = "Factory Default";
0029 gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
0030 linux,code = <KEY_RESTART>;
0031 };
0032 };
0033
0034 memory {
0035 device_type = "memory";
0036 reg = <0x00000000 0x08000000>; /* 128 MB */
0037 };
0038
0039 soc {
0040 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
0041 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
0042 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
0043 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
0044 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
0045
0046 internal-regs {
0047 rtc@a3800 {
0048 /*
0049 * If the rtc doesn't work, run "date reset"
0050 * twice in u-boot.
0051 */
0052 status = "okay";
0053 };
0054 };
0055 };
0056 };
0057
0058 ð0 {
0059 /* ethernet@70000 */
0060 bm,pool-long = <0>;
0061 bm,pool-short = <1>;
0062 buffer-manager = <&bm>;
0063 phy-mode = "rgmii-id";
0064 pinctrl-0 = <&ge0_rgmii_pins>;
0065 pinctrl-names = "default";
0066 status = "okay";
0067
0068 fixed-link {
0069 full-duplex;
0070 pause;
0071 speed = <1000>;
0072 };
0073 };
0074
0075 &mdio {
0076 pinctrl-names = "default";
0077 pinctrl-0 = <&mdio_pins>;
0078 status = "okay";
0079
0080 switch@0 {
0081 compatible = "marvell,mv88e6190";
0082 #address-cells = <1>;
0083 #interrupt-cells = <2>;
0084 interrupt-controller;
0085 interrupt-parent = <&gpio1>;
0086 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
0087 pinctrl-0 = <&switch_interrupt_pins>;
0088 pinctrl-names = "default";
0089 #size-cells = <0>;
0090 reg = <0>;
0091
0092 mdio {
0093 #address-cells = <1>;
0094 #size-cells = <0>;
0095
0096 switch0phy1: switch0phy1@1 {
0097 reg = <0x1>;
0098 };
0099
0100 switch0phy2: switch0phy2@2 {
0101 reg = <0x2>;
0102 };
0103
0104 switch0phy3: switch0phy3@3 {
0105 reg = <0x3>;
0106 };
0107
0108 switch0phy4: switch0phy4@4 {
0109 reg = <0x4>;
0110 };
0111
0112 switch0phy5: switch0phy5@5 {
0113 reg = <0x5>;
0114 };
0115
0116 switch0phy6: switch0phy6@6 {
0117 reg = <0x6>;
0118 };
0119
0120 switch0phy7: switch0phy7@7 {
0121 reg = <0x7>;
0122 };
0123
0124 switch0phy8: switch0phy8@8 {
0125 reg = <0x8>;
0126 };
0127 };
0128
0129 mdio-external {
0130 compatible = "marvell,mv88e6xxx-mdio-external";
0131 #address-cells = <1>;
0132 #size-cells = <0>;
0133
0134 phy1: ethernet-phy@b {
0135 reg = <0xb>;
0136 compatible = "ethernet-phy-ieee802.3-c45";
0137 };
0138
0139 phy2: ethernet-phy@c {
0140 reg = <0xc>;
0141 compatible = "ethernet-phy-ieee802.3-c45";
0142 };
0143 };
0144
0145 ports {
0146 #address-cells = <1>;
0147 #size-cells = <0>;
0148
0149 port@0 {
0150 ethernet = <ð0>;
0151 label = "cpu";
0152 reg = <0>;
0153
0154 fixed-link {
0155 full-duplex;
0156 pause;
0157 speed = <1000>;
0158 };
0159 };
0160
0161 port@1 {
0162 label = "lan1";
0163 phy-handle = <&switch0phy1>;
0164 reg = <1>;
0165 };
0166
0167 port@2 {
0168 label = "lan2";
0169 phy-handle = <&switch0phy2>;
0170 reg = <2>;
0171 };
0172
0173 port@3 {
0174 label = "lan3";
0175 phy-handle = <&switch0phy3>;
0176 reg = <3>;
0177 };
0178
0179 port@4 {
0180 label = "lan4";
0181 phy-handle = <&switch0phy4>;
0182 reg = <4>;
0183 };
0184
0185 port@5 {
0186 label = "lan5";
0187 phy-handle = <&switch0phy5>;
0188 reg = <5>;
0189 };
0190
0191 port@6 {
0192 label = "lan6";
0193 phy-handle = <&switch0phy6>;
0194 reg = <6>;
0195 };
0196
0197 port@7 {
0198 label = "lan7";
0199 phy-handle = <&switch0phy7>;
0200 reg = <7>;
0201 };
0202
0203 port@8 {
0204 label = "lan8";
0205 phy-handle = <&switch0phy8>;
0206 reg = <8>;
0207 };
0208
0209 port@9 {
0210 /* 88X3310P external phy */
0211 label = "lan9";
0212 phy-handle = <&phy1>;
0213 phy-mode = "xaui";
0214 reg = <9>;
0215 };
0216
0217 port@a {
0218 /* 88X3310P external phy */
0219 label = "lan10";
0220 phy-handle = <&phy2>;
0221 phy-mode = "xaui";
0222 reg = <0xa>;
0223 };
0224 };
0225 };
0226 };
0227
0228 &pinctrl {
0229 front_button_pins: front-button-pins {
0230 marvell,pins = "mpp38";
0231 marvell,function = "gpio";
0232 };
0233
0234 switch_interrupt_pins: switch-interrupt-pins {
0235 marvell,pins = "mpp39";
0236 marvell,function = "gpio";
0237 };
0238 };
0239
0240 &spi0 {
0241 pinctrl-0 = <&spi0_pins>;
0242 pinctrl-names = "default";
0243 status = "okay";
0244
0245 flash@0 {
0246 #address-cells = <1>;
0247 #size-cells = <1>;
0248 compatible = "jedec,spi-nor";
0249 reg = <0>; /* Chip select 0 */
0250 spi-max-frequency = <3000000>;
0251
0252 partitions {
0253 compatible = "fixed-partitions";
0254 #address-cells = <1>;
0255 #size-cells = <1>;
0256
0257 partition@0 {
0258 label = "boot";
0259 read-only;
0260 reg = <0x00000000 0x00100000>;
0261 };
0262
0263 partition@100000 {
0264 label = "env";
0265 reg = <0x00100000 0x00010000>;
0266 };
0267
0268 partition@200000 {
0269 label = "rsv";
0270 reg = <0x00110000 0x00010000>;
0271 };
0272
0273 partition@300000 {
0274 label = "image0";
0275 reg = <0x00120000 0x00900000>;
0276 };
0277
0278 partition@400000 {
0279 label = "config";
0280 reg = <0x00a20000 0x00300000>;
0281 };
0282
0283 partition@480000 {
0284 label = "debug";
0285 reg = <0x00d20000 0x002e0000>;
0286 };
0287 };
0288 };
0289 };
0290
0291 &uart0 {
0292 pinctrl-0 = <&uart0_pins>;
0293 pinctrl-names = "default";
0294 status = "okay";
0295 };
