0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Marvell Armada 380 SoC.
0004 *
0005 * Copyright (C) 2014 Marvell
0006 *
0007 * Lior Amsalem <alior@marvell.com>
0008 * Gregory CLEMENT <gregory.clement@free-electrons.com>
0009 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0010 */
0011
0012 #include "armada-38x.dtsi"
0013
0014 / {
0015 model = "Marvell Armada 380 family SoC";
0016 compatible = "marvell,armada380";
0017
0018 cpus {
0019 #address-cells = <1>;
0020 #size-cells = <0>;
0021 enable-method = "marvell,armada-380-smp";
0022
0023 cpu@0 {
0024 device_type = "cpu";
0025 compatible = "arm,cortex-a9";
0026 reg = <0>;
0027 };
0028 };
0029
0030 soc {
0031 internal-regs {
0032 pinctrl@18000 {
0033 compatible = "marvell,mv88f6810-pinctrl";
0034 };
0035 };
0036
0037 pcie {
0038 compatible = "marvell,armada-370-pcie";
0039 status = "disabled";
0040 device_type = "pci";
0041
0042 #address-cells = <3>;
0043 #size-cells = <2>;
0044
0045 msi-parent = <&mpic>;
0046 bus-range = <0x00 0xff>;
0047
0048 ranges =
0049 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
0050 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0051 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
0052 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
0053 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
0054 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
0055 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
0056 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
0057 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
0058 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
0059
0060 /* x1 port */
0061 pcie@1,0 {
0062 device_type = "pci";
0063 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
0064 reg = <0x0800 0 0 0 0>;
0065 #address-cells = <3>;
0066 #size-cells = <2>;
0067 #interrupt-cells = <1>;
0068 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0069 0x81000000 0 0 0x81000000 0x1 0 1 0>;
0070 bus-range = <0x00 0xff>;
0071 interrupt-map-mask = <0 0 0 0>;
0072 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0073 marvell,pcie-port = <0>;
0074 marvell,pcie-lane = <0>;
0075 clocks = <&gateclk 8>;
0076 status = "disabled";
0077 };
0078
0079 /* x1 port */
0080 pcie@2,0 {
0081 device_type = "pci";
0082 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
0083 reg = <0x1000 0 0 0 0>;
0084 #address-cells = <3>;
0085 #size-cells = <2>;
0086 #interrupt-cells = <1>;
0087 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0088 0x81000000 0 0 0x81000000 0x2 0 1 0>;
0089 bus-range = <0x00 0xff>;
0090 interrupt-map-mask = <0 0 0 0>;
0091 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0092 marvell,pcie-port = <1>;
0093 marvell,pcie-lane = <0>;
0094 clocks = <&gateclk 5>;
0095 status = "disabled";
0096 };
0097
0098 /* x1 port */
0099 pcie@3,0 {
0100 device_type = "pci";
0101 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
0102 reg = <0x1800 0 0 0 0>;
0103 #address-cells = <3>;
0104 #size-cells = <2>;
0105 #interrupt-cells = <1>;
0106 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0107 0x81000000 0 0 0x81000000 0x3 0 1 0>;
0108 bus-range = <0x00 0xff>;
0109 interrupt-map-mask = <0 0 0 0>;
0110 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0111 marvell,pcie-port = <2>;
0112 marvell,pcie-lane = <0>;
0113 clocks = <&gateclk 6>;
0114 status = "disabled";
0115 };
0116 };
0117 };
0118 };
