0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Marvell Armada 375 family SoC
0004 *
0005 * Copyright (C) 2014 Marvell
0006 *
0007 * Gregory CLEMENT <gregory.clement@free-electrons.com>
0008 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0009 */
0010
0011 #include <dt-bindings/interrupt-controller/arm-gic.h>
0012 #include <dt-bindings/interrupt-controller/irq.h>
0013 #include <dt-bindings/phy/phy.h>
0014
0015 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
0016
0017 / {
0018 #address-cells = <1>;
0019 #size-cells = <1>;
0020
0021 model = "Marvell Armada 375 family SoC";
0022 compatible = "marvell,armada375";
0023
0024 aliases {
0025 gpio0 = &gpio0;
0026 gpio1 = &gpio1;
0027 gpio2 = &gpio2;
0028 serial0 = &uart0;
0029 serial1 = &uart1;
0030 };
0031
0032 clocks {
0033 /* 1 GHz fixed main PLL */
0034 mainpll: mainpll {
0035 compatible = "fixed-clock";
0036 #clock-cells = <0>;
0037 clock-frequency = <1000000000>;
0038 };
0039 /* 25 MHz reference crystal */
0040 refclk: oscillator {
0041 compatible = "fixed-clock";
0042 #clock-cells = <0>;
0043 clock-frequency = <25000000>;
0044 };
0045 };
0046
0047 cpus {
0048 #address-cells = <1>;
0049 #size-cells = <0>;
0050 enable-method = "marvell,armada-375-smp";
0051
0052 cpu0: cpu@0 {
0053 device_type = "cpu";
0054 compatible = "arm,cortex-a9";
0055 reg = <0>;
0056 };
0057 cpu1: cpu@1 {
0058 device_type = "cpu";
0059 compatible = "arm,cortex-a9";
0060 reg = <1>;
0061 };
0062 };
0063
0064 pmu {
0065 compatible = "arm,cortex-a9-pmu";
0066 interrupts-extended = <&mpic 3>;
0067 };
0068
0069 soc {
0070 compatible = "marvell,armada375-mbus", "simple-bus";
0071 #address-cells = <2>;
0072 #size-cells = <1>;
0073 controller = <&mbusc>;
0074 interrupt-parent = <&gic>;
0075 pcie-mem-aperture = <0xe0000000 0x8000000>;
0076 pcie-io-aperture = <0xe8000000 0x100000>;
0077
0078 bootrom {
0079 compatible = "marvell,bootrom";
0080 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
0081 };
0082
0083 devbus_bootcs: devbus-bootcs {
0084 compatible = "marvell,mvebu-devbus";
0085 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
0086 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
0087 #address-cells = <1>;
0088 #size-cells = <1>;
0089 clocks = <&coreclk 0>;
0090 status = "disabled";
0091 };
0092
0093 devbus_cs0: devbus-cs0 {
0094 compatible = "marvell,mvebu-devbus";
0095 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
0096 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
0097 #address-cells = <1>;
0098 #size-cells = <1>;
0099 clocks = <&coreclk 0>;
0100 status = "disabled";
0101 };
0102
0103 devbus_cs1: devbus-cs1 {
0104 compatible = "marvell,mvebu-devbus";
0105 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
0106 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
0107 #address-cells = <1>;
0108 #size-cells = <1>;
0109 clocks = <&coreclk 0>;
0110 status = "disabled";
0111 };
0112
0113 devbus_cs2: devbus-cs2 {
0114 compatible = "marvell,mvebu-devbus";
0115 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
0116 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
0117 #address-cells = <1>;
0118 #size-cells = <1>;
0119 clocks = <&coreclk 0>;
0120 status = "disabled";
0121 };
0122
0123 devbus_cs3: devbus-cs3 {
0124 compatible = "marvell,mvebu-devbus";
0125 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
0126 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
0127 #address-cells = <1>;
0128 #size-cells = <1>;
0129 clocks = <&coreclk 0>;
0130 status = "disabled";
0131 };
0132
0133 internal-regs {
0134 compatible = "simple-bus";
0135 #address-cells = <1>;
0136 #size-cells = <1>;
0137 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
0138
0139 L2: cache-controller@8000 {
0140 compatible = "arm,pl310-cache";
0141 reg = <0x8000 0x1000>;
0142 cache-unified;
0143 cache-level = <2>;
0144 arm,double-linefill-incr = <0>;
0145 arm,double-linefill-wrap = <0>;
0146 arm,double-linefill = <0>;
0147 prefetch-data = <1>;
0148 };
0149
0150 scu: scu@c000 {
0151 compatible = "arm,cortex-a9-scu";
0152 reg = <0xc000 0x58>;
0153 };
0154
0155 timer0: timer@c600 {
0156 compatible = "arm,cortex-a9-twd-timer";
0157 reg = <0xc600 0x20>;
0158 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
0159 clocks = <&coreclk 2>;
0160 };
0161
0162 gic: interrupt-controller@d000 {
0163 compatible = "arm,cortex-a9-gic";
0164 #interrupt-cells = <3>;
0165 #size-cells = <0>;
0166 interrupt-controller;
0167 reg = <0xd000 0x1000>,
0168 <0xc100 0x100>;
0169 };
0170
0171 mdio: mdio@c0054 {
0172 #address-cells = <1>;
0173 #size-cells = <0>;
0174 compatible = "marvell,orion-mdio";
0175 reg = <0xc0054 0x4>;
0176 clocks = <&gateclk 19>;
0177 };
0178
0179 /* Network controller */
0180 ethernet: ethernet@f0000 {
0181 compatible = "marvell,armada-375-pp2";
0182 reg = <0xf0000 0xa000>, /* Packet Processor regs */
0183 <0xc0000 0x3060>, /* LMS regs */
0184 <0xc4000 0x100>, /* eth0 regs */
0185 <0xc5000 0x100>; /* eth1 regs */
0186 clocks = <&gateclk 3>, <&gateclk 19>;
0187 clock-names = "pp_clk", "gop_clk";
0188 status = "disabled";
0189
0190 eth0: eth0 {
0191 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0192 port-id = <0>;
0193 status = "disabled";
0194 };
0195
0196 eth1: eth1 {
0197 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0198 port-id = <1>;
0199 status = "disabled";
0200 };
0201 };
0202
0203 rtc: rtc@10300 {
0204 compatible = "marvell,orion-rtc";
0205 reg = <0x10300 0x20>;
0206 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0207 };
0208
0209 spi0: spi@10600 {
0210 compatible = "marvell,armada-375-spi",
0211 "marvell,orion-spi";
0212 reg = <0x10600 0x50>;
0213 #address-cells = <1>;
0214 #size-cells = <0>;
0215 cell-index = <0>;
0216 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0217 clocks = <&coreclk 0>;
0218 status = "disabled";
0219 };
0220
0221 spi1: spi@10680 {
0222 compatible = "marvell,armada-375-spi",
0223 "marvell,orion-spi";
0224 reg = <0x10680 0x50>;
0225 #address-cells = <1>;
0226 #size-cells = <0>;
0227 cell-index = <1>;
0228 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0229 clocks = <&coreclk 0>;
0230 status = "disabled";
0231 };
0232
0233 i2c0: i2c@11000 {
0234 compatible = "marvell,mv64xxx-i2c";
0235 reg = <0x11000 0x20>;
0236 #address-cells = <1>;
0237 #size-cells = <0>;
0238 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0239 clocks = <&coreclk 0>;
0240 status = "disabled";
0241 };
0242
0243 i2c1: i2c@11100 {
0244 compatible = "marvell,mv64xxx-i2c";
0245 reg = <0x11100 0x20>;
0246 #address-cells = <1>;
0247 #size-cells = <0>;
0248 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0249 clocks = <&coreclk 0>;
0250 status = "disabled";
0251 };
0252
0253 uart0: serial@12000 {
0254 compatible = "snps,dw-apb-uart";
0255 reg = <0x12000 0x100>;
0256 reg-shift = <2>;
0257 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0258 reg-io-width = <1>;
0259 clocks = <&coreclk 0>;
0260 status = "disabled";
0261 };
0262
0263 uart1: serial@12100 {
0264 compatible = "snps,dw-apb-uart";
0265 reg = <0x12100 0x100>;
0266 reg-shift = <2>;
0267 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0268 reg-io-width = <1>;
0269 clocks = <&coreclk 0>;
0270 status = "disabled";
0271 };
0272
0273 pinctrl: pinctrl@18000 {
0274 compatible = "marvell,mv88f6720-pinctrl";
0275 reg = <0x18000 0x24>;
0276
0277 i2c0_pins: i2c0-pins {
0278 marvell,pins = "mpp14", "mpp15";
0279 marvell,function = "i2c0";
0280 };
0281
0282 i2c1_pins: i2c1-pins {
0283 marvell,pins = "mpp61", "mpp62";
0284 marvell,function = "i2c1";
0285 };
0286
0287 nand_pins: nand-pins {
0288 marvell,pins = "mpp0", "mpp1", "mpp2",
0289 "mpp3", "mpp4", "mpp5",
0290 "mpp6", "mpp7", "mpp8",
0291 "mpp9", "mpp10", "mpp11",
0292 "mpp12", "mpp13";
0293 marvell,function = "nand";
0294 };
0295
0296 sdio_pins: sdio-pins {
0297 marvell,pins = "mpp24", "mpp25", "mpp26",
0298 "mpp27", "mpp28", "mpp29";
0299 marvell,function = "sd";
0300 };
0301
0302 spi0_pins: spi0-pins {
0303 marvell,pins = "mpp0", "mpp1", "mpp4",
0304 "mpp5", "mpp8", "mpp9";
0305 marvell,function = "spi0";
0306 };
0307 };
0308
0309 gpio0: gpio@18100 {
0310 compatible = "marvell,orion-gpio";
0311 reg = <0x18100 0x40>;
0312 ngpios = <32>;
0313 gpio-controller;
0314 #gpio-cells = <2>;
0315 interrupt-controller;
0316 #interrupt-cells = <2>;
0317 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0318 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0319 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0320 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0321 };
0322
0323 gpio1: gpio@18140 {
0324 compatible = "marvell,orion-gpio";
0325 reg = <0x18140 0x40>;
0326 ngpios = <32>;
0327 gpio-controller;
0328 #gpio-cells = <2>;
0329 interrupt-controller;
0330 #interrupt-cells = <2>;
0331 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
0332 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0333 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
0334 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0335 };
0336
0337 gpio2: gpio@18180 {
0338 compatible = "marvell,orion-gpio";
0339 reg = <0x18180 0x40>;
0340 ngpios = <3>;
0341 gpio-controller;
0342 #gpio-cells = <2>;
0343 interrupt-controller;
0344 #interrupt-cells = <2>;
0345 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0346 };
0347
0348 systemc: system-controller@18200 {
0349 compatible = "marvell,armada-375-system-controller";
0350 reg = <0x18200 0x100>;
0351 };
0352
0353 gateclk: clock-gating-control@18220 {
0354 compatible = "marvell,armada-375-gating-clock";
0355 reg = <0x18220 0x4>;
0356 clocks = <&coreclk 0>;
0357 #clock-cells = <1>;
0358 };
0359
0360 usbcluster: usb-cluster@18400 {
0361 compatible = "marvell,armada-375-usb-cluster";
0362 reg = <0x18400 0x4>;
0363 #phy-cells = <1>;
0364 };
0365
0366 mbusc: mbus-controller@20000 {
0367 compatible = "marvell,mbus-controller";
0368 reg = <0x20000 0x100>, <0x20180 0x20>;
0369 };
0370
0371 mpic: interrupt-controller@20a00 {
0372 compatible = "marvell,mpic";
0373 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
0374 #interrupt-cells = <1>;
0375 #size-cells = <1>;
0376 interrupt-controller;
0377 msi-controller;
0378 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
0379 };
0380
0381 timer1: timer@20300 {
0382 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
0383 reg = <0x20300 0x30>, <0x21040 0x30>;
0384 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0385 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0386 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0387 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0388 <&mpic 5>,
0389 <&mpic 6>;
0390 clocks = <&coreclk 0>, <&refclk>;
0391 clock-names = "nbclk", "fixed";
0392 };
0393
0394 watchdog: watchdog@20300 {
0395 compatible = "marvell,armada-375-wdt";
0396 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
0397 clocks = <&coreclk 0>, <&refclk>;
0398 clock-names = "nbclk", "fixed";
0399 };
0400
0401 cpurst: cpurst@20800 {
0402 compatible = "marvell,armada-370-cpu-reset";
0403 reg = <0x20800 0x10>;
0404 };
0405
0406 coherencyfab: coherency-fabric@21010 {
0407 compatible = "marvell,armada-375-coherency-fabric";
0408 reg = <0x21010 0x1c>;
0409 };
0410
0411 usb0: usb@50000 {
0412 compatible = "marvell,orion-ehci";
0413 reg = <0x50000 0x500>;
0414 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0415 clocks = <&gateclk 18>;
0416 phys = <&usbcluster PHY_TYPE_USB2>;
0417 phy-names = "usb";
0418 status = "disabled";
0419 };
0420
0421 usb1: usb@54000 {
0422 compatible = "marvell,orion-ehci";
0423 reg = <0x54000 0x500>;
0424 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0425 clocks = <&gateclk 26>;
0426 status = "disabled";
0427 };
0428
0429 usb2: usb@58000 {
0430 compatible = "marvell,armada-375-xhci";
0431 reg = <0x58000 0x20000>,<0x5b880 0x80>;
0432 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0433 clocks = <&gateclk 16>;
0434 phys = <&usbcluster PHY_TYPE_USB3>;
0435 phy-names = "usb";
0436 status = "disabled";
0437 };
0438
0439 xor0: xor@60800 {
0440 compatible = "marvell,orion-xor";
0441 reg = <0x60800 0x100
0442 0x60A00 0x100>;
0443 clocks = <&gateclk 22>;
0444 status = "okay";
0445
0446 xor00 {
0447 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0448 dmacap,memcpy;
0449 dmacap,xor;
0450 };
0451 xor01 {
0452 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0453 dmacap,memcpy;
0454 dmacap,xor;
0455 dmacap,memset;
0456 };
0457 };
0458
0459 xor1: xor@60900 {
0460 compatible = "marvell,orion-xor";
0461 reg = <0x60900 0x100
0462 0x60b00 0x100>;
0463 clocks = <&gateclk 23>;
0464 status = "okay";
0465
0466 xor10 {
0467 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0468 dmacap,memcpy;
0469 dmacap,xor;
0470 };
0471 xor11 {
0472 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0473 dmacap,memcpy;
0474 dmacap,xor;
0475 dmacap,memset;
0476 };
0477 };
0478
0479 cesa: crypto@90000 {
0480 compatible = "marvell,armada-375-crypto";
0481 reg = <0x90000 0x10000>;
0482 reg-names = "regs";
0483 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0484 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0485 clocks = <&gateclk 30>, <&gateclk 31>,
0486 <&gateclk 28>, <&gateclk 29>;
0487 clock-names = "cesa0", "cesa1",
0488 "cesaz0", "cesaz1";
0489 marvell,crypto-srams = <&crypto_sram0>,
0490 <&crypto_sram1>;
0491 marvell,crypto-sram-size = <0x800>;
0492 };
0493
0494 sata: sata@a0000 {
0495 compatible = "marvell,armada-370-sata";
0496 reg = <0xa0000 0x5000>;
0497 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0498 clocks = <&gateclk 14>, <&gateclk 20>;
0499 clock-names = "0", "1";
0500 status = "disabled";
0501 };
0502
0503 nand_controller: nand-controller@d0000 {
0504 compatible = "marvell,armada370-nand-controller";
0505 reg = <0xd0000 0x54>;
0506 #address-cells = <1>;
0507 #size-cells = <0>;
0508 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0509 clocks = <&gateclk 11>;
0510 status = "disabled";
0511 };
0512
0513 sdio: mvsdio@d4000 {
0514 compatible = "marvell,orion-sdio";
0515 reg = <0xd4000 0x200>;
0516 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0517 clocks = <&gateclk 17>;
0518 bus-width = <4>;
0519 cap-sdio-irq;
0520 cap-sd-highspeed;
0521 cap-mmc-highspeed;
0522 status = "disabled";
0523 };
0524
0525 thermal: thermal@e8078 {
0526 compatible = "marvell,armada375-thermal";
0527 reg = <0xe8078 0x4>, <0xe807c 0x8>;
0528 status = "okay";
0529 };
0530
0531 coreclk: mvebu-sar@e8204 {
0532 compatible = "marvell,armada-375-core-clock";
0533 reg = <0xe8204 0x04>;
0534 #clock-cells = <1>;
0535 };
0536
0537 coredivclk: corediv-clock@e8250 {
0538 compatible = "marvell,armada-375-corediv-clock";
0539 reg = <0xe8250 0xc>;
0540 #clock-cells = <1>;
0541 clocks = <&mainpll>;
0542 clock-output-names = "nand";
0543 };
0544 };
0545
0546 pciec: pcie@82000000 {
0547 compatible = "marvell,armada-370-pcie";
0548 status = "disabled";
0549 device_type = "pci";
0550
0551 #address-cells = <3>;
0552 #size-cells = <2>;
0553
0554 msi-parent = <&mpic>;
0555 bus-range = <0x00 0xff>;
0556
0557 ranges =
0558 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0559 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
0560 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
0561 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
0562 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
0563 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
0564
0565 pcie0: pcie@1,0 {
0566 device_type = "pci";
0567 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
0568 reg = <0x0800 0 0 0 0>;
0569 #address-cells = <3>;
0570 #size-cells = <2>;
0571 #interrupt-cells = <1>;
0572 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0573 0x81000000 0 0 0x81000000 0x1 0 1 0>;
0574 bus-range = <0x00 0xff>;
0575 interrupt-map-mask = <0 0 0 0>;
0576 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0577 marvell,pcie-port = <0>;
0578 marvell,pcie-lane = <0>;
0579 clocks = <&gateclk 5>;
0580 status = "disabled";
0581 };
0582
0583 pcie1: pcie@2,0 {
0584 device_type = "pci";
0585 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
0586 reg = <0x1000 0 0 0 0>;
0587 #address-cells = <3>;
0588 #size-cells = <2>;
0589 #interrupt-cells = <1>;
0590 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0591 0x81000000 0 0 0x81000000 0x2 0 1 0>;
0592 bus-range = <0x00 0xff>;
0593 interrupt-map-mask = <0 0 0 0>;
0594 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0595 marvell,pcie-port = <0>;
0596 marvell,pcie-lane = <1>;
0597 clocks = <&gateclk 6>;
0598 status = "disabled";
0599 };
0600
0601 };
0602
0603 crypto_sram0: sa-sram0 {
0604 compatible = "mmio-sram";
0605 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
0606 clocks = <&gateclk 30>;
0607 #address-cells = <1>;
0608 #size-cells = <1>;
0609 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
0610 };
0611
0612 crypto_sram1: sa-sram1 {
0613 compatible = "mmio-sram";
0614 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
0615 clocks = <&gateclk 31>;
0616 #address-cells = <1>;
0617 #size-cells = <1>;
0618 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
0619 };
0620 };
0621 };
