0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Marvell Armada 370 family SoC
0004 *
0005 * Copyright (C) 2012 Marvell
0006 *
0007 * Lior Amsalem <alior@marvell.com>
0008 * Gregory CLEMENT <gregory.clement@free-electrons.com>
0009 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0010 *
0011 * Contains definitions specific to the Armada 370 SoC that are not
0012 * common to all Armada SoCs.
0013 */
0014
0015 #include "armada-370-xp.dtsi"
0016
0017 / {
0018 #address-cells = <1>;
0019 #size-cells = <1>;
0020
0021 model = "Marvell Armada 370 family SoC";
0022 compatible = "marvell,armada370", "marvell,armada-370-xp";
0023
0024 aliases {
0025 gpio0 = &gpio0;
0026 gpio1 = &gpio1;
0027 gpio2 = &gpio2;
0028 };
0029
0030 soc {
0031 compatible = "marvell,armada370-mbus", "simple-bus";
0032
0033 bootrom {
0034 compatible = "marvell,bootrom";
0035 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
0036 };
0037
0038 pciec: pcie@82000000 {
0039 compatible = "marvell,armada-370-pcie";
0040 status = "disabled";
0041 device_type = "pci";
0042
0043 #address-cells = <3>;
0044 #size-cells = <2>;
0045
0046 msi-parent = <&mpic>;
0047 bus-range = <0x00 0xff>;
0048
0049 ranges =
0050 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0051 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
0052 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0053 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0054 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0055 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
0056
0057 pcie0: pcie@1,0 {
0058 device_type = "pci";
0059 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
0060 reg = <0x0800 0 0 0 0>;
0061 #address-cells = <3>;
0062 #size-cells = <2>;
0063 #interrupt-cells = <1>;
0064 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0065 0x81000000 0 0 0x81000000 0x1 0 1 0>;
0066 bus-range = <0x00 0xff>;
0067 interrupt-map-mask = <0 0 0 0>;
0068 interrupt-map = <0 0 0 0 &mpic 58>;
0069 marvell,pcie-port = <0>;
0070 marvell,pcie-lane = <0>;
0071 clocks = <&gateclk 5>;
0072 status = "disabled";
0073 };
0074
0075 pcie2: pcie@2,0 {
0076 device_type = "pci";
0077 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
0078 reg = <0x1000 0 0 0 0>;
0079 #address-cells = <3>;
0080 #size-cells = <2>;
0081 #interrupt-cells = <1>;
0082 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0083 0x81000000 0 0 0x81000000 0x2 0 1 0>;
0084 bus-range = <0x00 0xff>;
0085 interrupt-map-mask = <0 0 0 0>;
0086 interrupt-map = <0 0 0 0 &mpic 62>;
0087 marvell,pcie-port = <1>;
0088 marvell,pcie-lane = <0>;
0089 clocks = <&gateclk 9>;
0090 status = "disabled";
0091 };
0092 };
0093
0094 internal-regs {
0095 L2: l2-cache@8000 {
0096 compatible = "marvell,aurora-outer-cache";
0097 reg = <0x08000 0x1000>;
0098 cache-id-part = <0x100>;
0099 cache-level = <2>;
0100 cache-unified;
0101 wt-override;
0102 };
0103
0104 gpio0: gpio@18100 {
0105 compatible = "marvell,armada-370-gpio",
0106 "marvell,orion-gpio";
0107 reg = <0x18100 0x40>, <0x181c0 0x08>;
0108 reg-names = "gpio", "pwm";
0109 ngpios = <32>;
0110 gpio-controller;
0111 #gpio-cells = <2>;
0112 #pwm-cells = <2>;
0113 interrupt-controller;
0114 #interrupt-cells = <2>;
0115 interrupts = <82>, <83>, <84>, <85>;
0116 clocks = <&coreclk 0>;
0117 };
0118
0119 gpio1: gpio@18140 {
0120 compatible = "marvell,armada-370-gpio",
0121 "marvell,orion-gpio";
0122 reg = <0x18140 0x40>, <0x181c8 0x08>;
0123 reg-names = "gpio", "pwm";
0124 ngpios = <32>;
0125 gpio-controller;
0126 #gpio-cells = <2>;
0127 #pwm-cells = <2>;
0128 interrupt-controller;
0129 #interrupt-cells = <2>;
0130 interrupts = <87>, <88>, <89>, <90>;
0131 clocks = <&coreclk 0>;
0132 };
0133
0134 gpio2: gpio@18180 {
0135 compatible = "marvell,armada-370-gpio",
0136 "marvell,orion-gpio";
0137 reg = <0x18180 0x40>;
0138 ngpios = <2>;
0139 gpio-controller;
0140 #gpio-cells = <2>;
0141 interrupt-controller;
0142 #interrupt-cells = <2>;
0143 interrupts = <91>;
0144 };
0145
0146
0147 systemc: system-controller@18200 {
0148 compatible = "marvell,armada-370-xp-system-controller";
0149 reg = <0x18200 0x100>;
0150 };
0151
0152 gateclk: clock-gating-control@18220 {
0153 compatible = "marvell,armada-370-gating-clock";
0154 reg = <0x18220 0x4>;
0155 clocks = <&coreclk 0>;
0156 #clock-cells = <1>;
0157 };
0158
0159 coreclk: mvebu-sar@18230 {
0160 compatible = "marvell,armada-370-core-clock";
0161 reg = <0x18230 0x08>;
0162 #clock-cells = <1>;
0163 };
0164
0165 thermal: thermal@18300 {
0166 compatible = "marvell,armada370-thermal";
0167 reg = <0x18300 0x4
0168 0x18304 0x4>;
0169 status = "okay";
0170 };
0171
0172 sscg: sscg@18330 {
0173 reg = <0x18330 0x4>;
0174 };
0175
0176 cpuconf: cpu-config@21000 {
0177 compatible = "marvell,armada-370-cpu-config";
0178 reg = <0x21000 0x8>;
0179 };
0180
0181 audio_controller: audio-controller@30000 {
0182 #sound-dai-cells = <1>;
0183 compatible = "marvell,armada370-audio";
0184 reg = <0x30000 0x4000>;
0185 interrupts = <93>;
0186 clocks = <&gateclk 0>;
0187 clock-names = "internal";
0188 status = "disabled";
0189 };
0190
0191 xor0: xor@60800 {
0192 compatible = "marvell,orion-xor";
0193 reg = <0x60800 0x100
0194 0x60A00 0x100>;
0195 status = "okay";
0196
0197 xor00 {
0198 interrupts = <51>;
0199 dmacap,memcpy;
0200 dmacap,xor;
0201 };
0202 xor01 {
0203 interrupts = <52>;
0204 dmacap,memcpy;
0205 dmacap,xor;
0206 dmacap,memset;
0207 };
0208 };
0209
0210 xor1: xor@60900 {
0211 compatible = "marvell,orion-xor";
0212 reg = <0x60900 0x100
0213 0x60b00 0x100>;
0214 status = "okay";
0215
0216 xor10 {
0217 interrupts = <94>;
0218 dmacap,memcpy;
0219 dmacap,xor;
0220 };
0221 xor11 {
0222 interrupts = <95>;
0223 dmacap,memcpy;
0224 dmacap,xor;
0225 dmacap,memset;
0226 };
0227 };
0228
0229 cesa: crypto@90000 {
0230 compatible = "marvell,armada-370-crypto";
0231 reg = <0x90000 0x10000>;
0232 reg-names = "regs";
0233 interrupts = <48>;
0234 clocks = <&gateclk 23>;
0235 clock-names = "cesa0";
0236 marvell,crypto-srams = <&crypto_sram>;
0237 marvell,crypto-sram-size = <0x7e0>;
0238 };
0239 };
0240
0241 crypto_sram: sa-sram {
0242 compatible = "mmio-sram";
0243 reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
0244 reg-names = "sram";
0245 clocks = <&gateclk 23>;
0246 #address-cells = <1>;
0247 #size-cells = <1>;
0248 ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;
0249
0250 /*
0251 * The Armada 370 has an erratum preventing the use of
0252 * the standard workflow for CPU idle support (relying
0253 * on the BootROM code to enter/exit idle state).
0254 * Reserve some amount of the crypto SRAM to put the
0255 * cpuidle workaround.
0256 */
0257 idle-sram@0 {
0258 reg = <0x0 0x20>;
0259 };
0260 };
0261 };
0262 };
0263
0264 /*
0265 * Default UART pinctrl setting without RTS/CTS, can be overwritten on
0266 * board level if a different configuration is used.
0267 */
0268
0269 &uart0 {
0270 pinctrl-0 = <&uart0_pins>;
0271 pinctrl-names = "default";
0272 };
0273
0274 &uart1 {
0275 pinctrl-0 = <&uart1_pins>;
0276 pinctrl-names = "default";
0277 };
0278
0279 &i2c0 {
0280 reg = <0x11000 0x20>;
0281 };
0282
0283 &i2c1 {
0284 reg = <0x11100 0x20>;
0285 };
0286
0287 &mpic {
0288 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
0289 };
0290
0291 &timer {
0292 compatible = "marvell,armada-370-timer";
0293 clocks = <&coreclk 2>;
0294 };
0295
0296 &watchdog {
0297 compatible = "marvell,armada-370-wdt";
0298 clocks = <&coreclk 2>;
0299 };
0300
0301 &usb0 {
0302 clocks = <&coreclk 0>;
0303 };
0304
0305 &usb1 {
0306 clocks = <&coreclk 0>;
0307 };
0308
0309 ð0 {
0310 compatible = "marvell,armada-370-neta";
0311 };
0312
0313 ð1 {
0314 compatible = "marvell,armada-370-neta";
0315 };
0316
0317 &pinctrl {
0318 compatible = "marvell,mv88f6710-pinctrl";
0319
0320 spi0_pins1: spi0-pins1 {
0321 marvell,pins = "mpp33", "mpp34",
0322 "mpp35", "mpp36";
0323 marvell,function = "spi0";
0324 };
0325
0326 spi0_pins2: spi0_pins2 {
0327 marvell,pins = "mpp32", "mpp63",
0328 "mpp64", "mpp65";
0329 marvell,function = "spi0";
0330 };
0331
0332 spi1_pins: spi1-pins {
0333 marvell,pins = "mpp49", "mpp50",
0334 "mpp51", "mpp52";
0335 marvell,function = "spi1";
0336 };
0337
0338 uart0_pins: uart0-pins {
0339 marvell,pins = "mpp0", "mpp1";
0340 marvell,function = "uart0";
0341 };
0342
0343 uart1_pins: uart1-pins {
0344 marvell,pins = "mpp41", "mpp42";
0345 marvell,function = "uart1";
0346 };
0347
0348 sdio_pins1: sdio-pins1 {
0349 marvell,pins = "mpp9", "mpp11", "mpp12",
0350 "mpp13", "mpp14", "mpp15";
0351 marvell,function = "sd0";
0352 };
0353
0354 sdio_pins2: sdio-pins2 {
0355 marvell,pins = "mpp47", "mpp48", "mpp49",
0356 "mpp50", "mpp51", "mpp52";
0357 marvell,function = "sd0";
0358 };
0359
0360 sdio_pins3: sdio-pins3 {
0361 marvell,pins = "mpp48", "mpp49", "mpp50",
0362 "mpp51", "mpp52", "mpp53";
0363 marvell,function = "sd0";
0364 };
0365
0366 i2c0_pins: i2c0-pins {
0367 marvell,pins = "mpp2", "mpp3";
0368 marvell,function = "i2c0";
0369 };
0370
0371 i2s_pins1: i2s-pins1 {
0372 marvell,pins = "mpp5", "mpp6", "mpp7",
0373 "mpp8", "mpp9", "mpp10",
0374 "mpp12", "mpp13";
0375 marvell,function = "audio";
0376 };
0377
0378 i2s_pins2: i2s-pins2 {
0379 marvell,pins = "mpp49", "mpp47", "mpp50",
0380 "mpp59", "mpp57", "mpp61",
0381 "mpp62", "mpp60", "mpp58";
0382 marvell,function = "audio";
0383 };
0384
0385 mdio_pins: mdio-pins {
0386 marvell,pins = "mpp17", "mpp18";
0387 marvell,function = "ge";
0388 };
0389
0390 ge0_rgmii_pins: ge0-rgmii-pins {
0391 marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
0392 "mpp9", "mpp10", "mpp11", "mpp12",
0393 "mpp13", "mpp14", "mpp15", "mpp16";
0394 marvell,function = "ge0";
0395 };
0396
0397 ge1_rgmii_pins: ge1-rgmii-pins {
0398 marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
0399 "mpp23", "mpp24", "mpp25", "mpp26",
0400 "mpp27", "mpp28", "mpp29", "mpp30";
0401 marvell,function = "ge1";
0402 };
0403 };
0404
0405 /*
0406 * Default SPI pinctrl setting, can be overwritten on
0407 * board level if a different configuration is used.
0408 */
0409 &spi0 {
0410 compatible = "marvell,armada-370-spi", "marvell,orion-spi";
0411 pinctrl-0 = <&spi0_pins1>;
0412 pinctrl-names = "default";
0413 };
0414
0415 &spi1 {
0416 compatible = "marvell,armada-370-spi", "marvell,orion-spi";
0417 pinctrl-0 = <&spi1_pins>;
0418 pinctrl-names = "default";
0419 };
