0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
0004 *
0005 * Copyright (C) 2012 Marvell
0006 *
0007 * Lior Amsalem <alior@marvell.com>
0008 * Gregory CLEMENT <gregory.clement@free-electrons.com>
0009 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0010 * Ben Dooks <ben.dooks@codethink.co.uk>
0011 *
0012 * This file contains the definitions that are common to the Armada
0013 * 370 and Armada XP SoC.
0014 */
0015
0016 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
0017
0018 / {
0019 model = "Marvell Armada 370 and XP SoC";
0020 compatible = "marvell,armada-370-xp";
0021
0022 aliases {
0023 serial0 = &uart0;
0024 serial1 = &uart1;
0025 };
0026
0027 cpus {
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030 cpu@0 {
0031 compatible = "marvell,sheeva-v7";
0032 device_type = "cpu";
0033 reg = <0>;
0034 };
0035 };
0036
0037 pmu {
0038 compatible = "arm,cortex-a9-pmu";
0039 interrupts-extended = <&mpic 3>;
0040 };
0041
0042 soc {
0043 #address-cells = <2>;
0044 #size-cells = <1>;
0045 controller = <&mbusc>;
0046 interrupt-parent = <&mpic>;
0047 pcie-mem-aperture = <0xf8000000 0x7e00000>;
0048 pcie-io-aperture = <0xffe00000 0x100000>;
0049
0050 devbus_bootcs: devbus-bootcs {
0051 compatible = "marvell,mvebu-devbus";
0052 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
0053 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
0054 #address-cells = <1>;
0055 #size-cells = <1>;
0056 clocks = <&coreclk 0>;
0057 status = "disabled";
0058 };
0059
0060 devbus_cs0: devbus-cs0 {
0061 compatible = "marvell,mvebu-devbus";
0062 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
0063 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
0064 #address-cells = <1>;
0065 #size-cells = <1>;
0066 clocks = <&coreclk 0>;
0067 status = "disabled";
0068 };
0069
0070 devbus_cs1: devbus-cs1 {
0071 compatible = "marvell,mvebu-devbus";
0072 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
0073 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
0074 #address-cells = <1>;
0075 #size-cells = <1>;
0076 clocks = <&coreclk 0>;
0077 status = "disabled";
0078 };
0079
0080 devbus_cs2: devbus-cs2 {
0081 compatible = "marvell,mvebu-devbus";
0082 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
0083 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
0084 #address-cells = <1>;
0085 #size-cells = <1>;
0086 clocks = <&coreclk 0>;
0087 status = "disabled";
0088 };
0089
0090 devbus_cs3: devbus-cs3 {
0091 compatible = "marvell,mvebu-devbus";
0092 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
0093 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
0094 #address-cells = <1>;
0095 #size-cells = <1>;
0096 clocks = <&coreclk 0>;
0097 status = "disabled";
0098 };
0099
0100 internal-regs {
0101 compatible = "simple-bus";
0102 #address-cells = <1>;
0103 #size-cells = <1>;
0104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
0105
0106 rtc: rtc@10300 {
0107 compatible = "marvell,orion-rtc";
0108 reg = <0x10300 0x20>;
0109 interrupts = <50>;
0110 };
0111
0112 i2c0: i2c@11000 {
0113 compatible = "marvell,mv64xxx-i2c";
0114 #address-cells = <1>;
0115 #size-cells = <0>;
0116 interrupts = <31>;
0117 clocks = <&coreclk 0>;
0118 status = "disabled";
0119 };
0120
0121 i2c1: i2c@11100 {
0122 compatible = "marvell,mv64xxx-i2c";
0123 #address-cells = <1>;
0124 #size-cells = <0>;
0125 interrupts = <32>;
0126 clocks = <&coreclk 0>;
0127 status = "disabled";
0128 };
0129
0130 uart0: serial@12000 {
0131 compatible = "snps,dw-apb-uart";
0132 reg = <0x12000 0x100>;
0133 reg-shift = <2>;
0134 interrupts = <41>;
0135 reg-io-width = <1>;
0136 clocks = <&coreclk 0>;
0137 status = "disabled";
0138 };
0139
0140 uart1: serial@12100 {
0141 compatible = "snps,dw-apb-uart";
0142 reg = <0x12100 0x100>;
0143 reg-shift = <2>;
0144 interrupts = <42>;
0145 reg-io-width = <1>;
0146 clocks = <&coreclk 0>;
0147 status = "disabled";
0148 };
0149
0150 pinctrl: pin-ctrl@18000 {
0151 reg = <0x18000 0x38>;
0152 };
0153
0154 coredivclk: corediv-clock@18740 {
0155 compatible = "marvell,armada-370-corediv-clock";
0156 reg = <0x18740 0xc>;
0157 #clock-cells = <1>;
0158 clocks = <&mainpll>;
0159 clock-output-names = "nand";
0160 };
0161
0162 mbusc: mbus-controller@20000 {
0163 compatible = "marvell,mbus-controller";
0164 reg = <0x20000 0x100>, <0x20180 0x20>,
0165 <0x20250 0x8>;
0166 };
0167
0168 mpic: interrupt-controller@20a00 {
0169 compatible = "marvell,mpic";
0170 #interrupt-cells = <1>;
0171 #size-cells = <1>;
0172 interrupt-controller;
0173 msi-controller;
0174 };
0175
0176 coherencyfab: coherency-fabric@20200 {
0177 compatible = "marvell,coherency-fabric";
0178 reg = <0x20200 0xb0>, <0x21010 0x1c>;
0179 };
0180
0181 timer: timer@20300 {
0182 reg = <0x20300 0x30>, <0x21040 0x30>;
0183 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
0184 };
0185
0186 watchdog: watchdog@20300 {
0187 reg = <0x20300 0x34>, <0x20704 0x4>;
0188 };
0189
0190 cpurst: cpurst@20800 {
0191 compatible = "marvell,armada-370-cpu-reset";
0192 reg = <0x20800 0x8>;
0193 };
0194
0195 pmsu: pmsu@22000 {
0196 compatible = "marvell,armada-370-pmsu";
0197 reg = <0x22000 0x1000>;
0198 };
0199
0200 usb0: usb@50000 {
0201 compatible = "marvell,orion-ehci";
0202 reg = <0x50000 0x500>;
0203 interrupts = <45>;
0204 status = "disabled";
0205 };
0206
0207 usb1: usb@51000 {
0208 compatible = "marvell,orion-ehci";
0209 reg = <0x51000 0x500>;
0210 interrupts = <46>;
0211 status = "disabled";
0212 };
0213
0214 eth0: ethernet@70000 {
0215 reg = <0x70000 0x4000>;
0216 interrupts = <8>;
0217 clocks = <&gateclk 4>;
0218 status = "disabled";
0219 };
0220
0221 mdio: mdio@72004 {
0222 #address-cells = <1>;
0223 #size-cells = <0>;
0224 compatible = "marvell,orion-mdio";
0225 reg = <0x72004 0x4>;
0226 clocks = <&gateclk 4>;
0227 };
0228
0229 eth1: ethernet@74000 {
0230 reg = <0x74000 0x4000>;
0231 interrupts = <10>;
0232 clocks = <&gateclk 3>;
0233 status = "disabled";
0234 };
0235
0236 sata: sata@a0000 {
0237 compatible = "marvell,armada-370-sata";
0238 reg = <0xa0000 0x5000>;
0239 interrupts = <55>;
0240 clocks = <&gateclk 15>, <&gateclk 30>;
0241 clock-names = "0", "1";
0242 status = "disabled";
0243 };
0244
0245 nand_controller: nand-controller@d0000 {
0246 compatible = "marvell,armada370-nand-controller";
0247 reg = <0xd0000 0x54>;
0248 #address-cells = <1>;
0249 #size-cells = <0>;
0250 interrupts = <113>;
0251 clocks = <&coredivclk 0>;
0252 status = "disabled";
0253 };
0254
0255 sdio: mvsdio@d4000 {
0256 compatible = "marvell,orion-sdio";
0257 reg = <0xd4000 0x200>;
0258 interrupts = <54>;
0259 clocks = <&gateclk 17>;
0260 bus-width = <4>;
0261 cap-sdio-irq;
0262 cap-sd-highspeed;
0263 cap-mmc-highspeed;
0264 status = "disabled";
0265 };
0266 };
0267
0268 spi0: spi@10600 {
0269 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
0270 <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
0271 <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
0272 <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
0273 <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
0274 <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
0275 <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
0276 <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
0277 <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
0278 #address-cells = <1>;
0279 #size-cells = <0>;
0280 cell-index = <0>;
0281 interrupts = <30>;
0282 clocks = <&coreclk 0>;
0283 status = "disabled";
0284 };
0285
0286 spi1: spi@10680 {
0287 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
0288 <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
0289 <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
0290 <MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
0291 <MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
0292 <MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
0293 <MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
0294 <MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
0295 <MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
0296 #address-cells = <1>;
0297 #size-cells = <0>;
0298 cell-index = <1>;
0299 interrupts = <92>;
0300 clocks = <&coreclk 0>;
0301 status = "disabled";
0302 };
0303 };
0304
0305 clocks {
0306 /* 2 GHz fixed main PLL */
0307 mainpll: mainpll {
0308 compatible = "fixed-clock";
0309 #clock-cells = <0>;
0310 clock-frequency = <2000000000>;
0311 };
0312 };
0313 };
