0001 /*
0002 * Copyright 2016 Linaro Ltd
0003 *
0004 * Permission is hereby granted, free of charge, to any person obtaining a copy
0005 * of this software and associated documentation files (the "Software"), to deal
0006 * in the Software without restriction, including without limitation the rights
0007 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
0008 * copies of the Software, and to permit persons to whom the Software is
0009 * furnished to do so, subject to the following conditions:
0010 *
0011 * The above copyright notice and this permission notice shall be included in
0012 * all copies or substantial portions of the Software.
0013 *
0014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
0017 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0019 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
0020 * THE SOFTWARE.
0021 */
0022
0023 #include <dt-bindings/interrupt-controller/irq.h>
0024 #include <dt-bindings/gpio/gpio.h>
0025
0026 / {
0027 #address-cells = <1>;
0028 #size-cells = <1>;
0029 compatible = "arm,realview-pbx";
0030
0031 chosen { };
0032
0033 aliases {
0034 serial0 = &serial0;
0035 serial1 = &serial1;
0036 serial2 = &serial2;
0037 serial3 = &serial3;
0038 i2c0 = &i2c0;
0039 i2c1 = &i2c1;
0040 };
0041
0042 memory {
0043 device_type = "memory";
0044 /* 128 MiB memory @ 0x0 */
0045 reg = <0x00000000 0x08000000>;
0046 };
0047
0048 /* The voltage to the MMC card is hardwired at 3.3V */
0049 vmmc: regulator-vmmc {
0050 compatible = "regulator-fixed";
0051 regulator-name = "vmmc";
0052 regulator-min-microvolt = <3300000>;
0053 regulator-max-microvolt = <3300000>;
0054 regulator-boot-on;
0055 };
0056
0057 veth: regulator-veth {
0058 compatible = "regulator-fixed";
0059 regulator-name = "veth";
0060 regulator-min-microvolt = <3300000>;
0061 regulator-max-microvolt = <3300000>;
0062 regulator-boot-on;
0063 };
0064
0065 xtal24mhz: xtal24mhz@24M {
0066 #clock-cells = <0>;
0067 compatible = "fixed-clock";
0068 clock-frequency = <24000000>;
0069 };
0070
0071 refclk32khz: refclk32khz {
0072 #clock-cells = <0>;
0073 compatible = "fixed-clock";
0074 clock-frequency = <32768>;
0075 };
0076
0077 timclk: timclk@1M {
0078 #clock-cells = <0>;
0079 compatible = "fixed-factor-clock";
0080 clock-div = <24>;
0081 clock-mult = <1>;
0082 clocks = <&xtal24mhz>;
0083 };
0084
0085 mclk: mclk@24M {
0086 #clock-cells = <0>;
0087 compatible = "fixed-factor-clock";
0088 clock-div = <1>;
0089 clock-mult = <1>;
0090 clocks = <&xtal24mhz>;
0091 };
0092
0093 kmiclk: kmiclk@24M {
0094 #clock-cells = <0>;
0095 compatible = "fixed-factor-clock";
0096 clock-div = <1>;
0097 clock-mult = <1>;
0098 clocks = <&xtal24mhz>;
0099 };
0100
0101 sspclk: sspclk@24M {
0102 #clock-cells = <0>;
0103 compatible = "fixed-factor-clock";
0104 clock-div = <1>;
0105 clock-mult = <1>;
0106 clocks = <&xtal24mhz>;
0107 };
0108
0109 uartclk: uartclk@24M {
0110 #clock-cells = <0>;
0111 compatible = "fixed-factor-clock";
0112 clock-div = <1>;
0113 clock-mult = <1>;
0114 clocks = <&xtal24mhz>;
0115 };
0116
0117 wdogclk: wdogclk@24M {
0118 #clock-cells = <0>;
0119 compatible = "fixed-factor-clock";
0120 clock-div = <1>;
0121 clock-mult = <1>;
0122 clocks = <&xtal24mhz>;
0123 };
0124
0125 /* FIXME: this actually hangs off the PLL clocks */
0126 pclk: pclk@0 {
0127 #clock-cells = <0>;
0128 compatible = "fixed-clock";
0129 clock-frequency = <0>;
0130 };
0131
0132 flash0@40000000 {
0133 /* 2 * 32MiB NOR Flash memory */
0134 compatible = "arm,versatile-flash", "cfi-flash";
0135 reg = <0x40000000 0x04000000>;
0136 bank-width = <4>;
0137 partitions {
0138 compatible = "arm,arm-firmware-suite";
0139 };
0140 };
0141
0142 flash1@44000000 {
0143 /* 2 * 32MiB NOR Flash memory */
0144 compatible = "arm,versatile-flash", "cfi-flash";
0145 reg = <0x44000000 0x04000000>;
0146 bank-width = <4>;
0147 partitions {
0148 compatible = "arm,arm-firmware-suite";
0149 };
0150 };
0151
0152 /* SMSC 9118 ethernet with PHY and EEPROM */
0153 ethernet: ethernet@4e000000 {
0154 compatible = "smsc,lan9118", "smsc,lan9115";
0155 reg = <0x4e000000 0x10000>;
0156 phy-mode = "mii";
0157 reg-io-width = <4>;
0158 smsc,irq-active-high;
0159 smsc,irq-push-pull;
0160 vdd33a-supply = <&veth>;
0161 vddvario-supply = <&veth>;
0162 };
0163
0164 usb: usb@4f000000 {
0165 compatible = "nxp,usb-isp1761";
0166 reg = <0x4f000000 0x20000>;
0167 dr_mode = "peripheral";
0168 };
0169
0170 bridge {
0171 compatible = "ti,ths8134a", "ti,ths8134";
0172 #address-cells = <1>;
0173 #size-cells = <0>;
0174
0175 ports {
0176 #address-cells = <1>;
0177 #size-cells = <0>;
0178
0179 port@0 {
0180 reg = <0>;
0181
0182 vga_bridge_in: endpoint {
0183 remote-endpoint = <&clcd_pads>;
0184 };
0185 };
0186
0187 port@1 {
0188 reg = <1>;
0189
0190 vga_bridge_out: endpoint {
0191 remote-endpoint = <&vga_con_in>;
0192 };
0193 };
0194 };
0195 };
0196
0197 vga {
0198 /*
0199 * This DDC I2C is connected directly to the DVI portions
0200 * of the connector, so it's not really working when the
0201 * monitor is connected to the VGA connector.
0202 */
0203 compatible = "vga-connector";
0204 ddc-i2c-bus = <&i2c1>;
0205
0206 port {
0207 vga_con_in: endpoint {
0208 remote-endpoint = <&vga_bridge_out>;
0209 };
0210 };
0211 };
0212
0213 soc: soc {
0214 compatible = "arm,realview-pbx-soc", "simple-bus";
0215 #address-cells = <1>;
0216 #size-cells = <1>;
0217 regmap = <&syscon>;
0218 ranges;
0219
0220 syscon: syscon@10000000 {
0221 compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
0222 reg = <0x10000000 0x1000>;
0223 ranges = <0x0 0x10000000 0x1000>;
0224 #address-cells = <1>;
0225 #size-cells = <1>;
0226
0227 led@8,0 {
0228 compatible = "register-bit-led";
0229 reg = <0x08 0x04>;
0230 offset = <0x08>;
0231 mask = <0x01>;
0232 label = "versatile:0";
0233 linux,default-trigger = "heartbeat";
0234 default-state = "on";
0235 };
0236 led@8,1 {
0237 compatible = "register-bit-led";
0238 reg = <0x08 0x04>;
0239 offset = <0x08>;
0240 mask = <0x02>;
0241 label = "versatile:1";
0242 linux,default-trigger = "mmc0";
0243 default-state = "off";
0244 };
0245 led@8,2 {
0246 compatible = "register-bit-led";
0247 reg = <0x08 0x04>;
0248 offset = <0x08>;
0249 mask = <0x04>;
0250 label = "versatile:2";
0251 linux,default-trigger = "cpu0";
0252 default-state = "off";
0253 };
0254 led@8,3 {
0255 compatible = "register-bit-led";
0256 reg = <0x08 0x04>;
0257 offset = <0x08>;
0258 mask = <0x08>;
0259 label = "versatile:3";
0260 default-state = "off";
0261 };
0262 led@8,4 {
0263 compatible = "register-bit-led";
0264 reg = <0x08 0x04>;
0265 offset = <0x08>;
0266 mask = <0x10>;
0267 label = "versatile:4";
0268 default-state = "off";
0269 };
0270 led@8,5 {
0271 compatible = "register-bit-led";
0272 reg = <0x08 0x04>;
0273 offset = <0x08>;
0274 mask = <0x20>;
0275 label = "versatile:5";
0276 default-state = "off";
0277 };
0278 led@8,6 {
0279 compatible = "register-bit-led";
0280 reg = <0x08 0x04>;
0281 offset = <0x08>;
0282 mask = <0x40>;
0283 label = "versatile:6";
0284 default-state = "off";
0285 };
0286 led@8,7 {
0287 compatible = "register-bit-led";
0288 reg = <0x08 0x04>;
0289 offset = <0x08>;
0290 mask = <0x80>;
0291 label = "versatile:7";
0292 default-state = "off";
0293 };
0294 oscclk0: clock-controller@c {
0295 compatible = "arm,syscon-icst307";
0296 reg = <0x0c 0x04>;
0297 #clock-cells = <0>;
0298 lock-offset = <0x20>;
0299 vco-offset = <0x0C>;
0300 clocks = <&xtal24mhz>;
0301 };
0302 oscclk1: clock-controller@10 {
0303 compatible = "arm,syscon-icst307";
0304 reg = <0x10 0x04>;
0305 #clock-cells = <0>;
0306 lock-offset = <0x20>;
0307 vco-offset = <0x10>;
0308 clocks = <&xtal24mhz>;
0309 };
0310 oscclk2: clock-controller@14 {
0311 compatible = "arm,syscon-icst307";
0312 reg = <0x14 0x04>;
0313 #clock-cells = <0>;
0314 lock-offset = <0x20>;
0315 vco-offset = <0x14>;
0316 clocks = <&xtal24mhz>;
0317 };
0318 oscclk3: clock-controller@18 {
0319 compatible = "arm,syscon-icst307";
0320 reg = <0x18 0x04>;
0321 #clock-cells = <0>;
0322 lock-offset = <0x20>;
0323 vco-offset = <0x18>;
0324 clocks = <&xtal24mhz>;
0325 };
0326 oscclk4: clock-controller@1c {
0327 compatible = "arm,syscon-icst307";
0328 reg = <0x1c 0x04>;
0329 #clock-cells = <0>;
0330 lock-offset = <0x20>;
0331 vco-offset = <0x1c>;
0332 clocks = <&xtal24mhz>;
0333 };
0334 };
0335
0336 sp810_syscon0: sysctl@10001000 {
0337 compatible = "arm,sp810", "arm,primecell";
0338 reg = <0x10001000 0x1000>;
0339 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
0340 clock-names = "refclk", "timclk", "apb_pclk";
0341 #clock-cells = <1>;
0342 clock-output-names = "timerclk0",
0343 "timerclk1",
0344 "timerclk2",
0345 "timerclk3";
0346 assigned-clocks = <&sp810_syscon0 0>,
0347 <&sp810_syscon0 1>,
0348 <&sp810_syscon0 2>,
0349 <&sp810_syscon0 3>;
0350 assigned-clock-parents = <&timclk>,
0351 <&timclk>,
0352 <&timclk>,
0353 <&timclk>;
0354 };
0355
0356 i2c0: i2c@10002000 {
0357 #address-cells = <1>;
0358 #size-cells = <0>;
0359 compatible = "arm,versatile-i2c";
0360 reg = <0x10002000 0x1000>;
0361
0362 rtc@68 {
0363 compatible = "dallas,ds1338";
0364 reg = <0x68>;
0365 };
0366 };
0367
0368 serial0: serial@10009000 {
0369 compatible = "arm,pl011", "arm,primecell";
0370 reg = <0x10009000 0x1000>;
0371 clocks = <&uartclk>, <&pclk>;
0372 clock-names = "uartclk", "apb_pclk";
0373 };
0374
0375 serial1: serial@1000a000 {
0376 compatible = "arm,pl011", "arm,primecell";
0377 reg = <0x1000a000 0x1000>;
0378 clocks = <&uartclk>, <&pclk>;
0379 clock-names = "uartclk", "apb_pclk";
0380 };
0381
0382 serial2: serial@1000b000 {
0383 compatible = "arm,pl011", "arm,primecell";
0384 reg = <0x1000b000 0x1000>;
0385 clocks = <&uartclk>, <&pclk>;
0386 clock-names = "uartclk", "apb_pclk";
0387 };
0388
0389 ssp: spi@1000d000 {
0390 compatible = "arm,pl022", "arm,primecell";
0391 reg = <0x1000d000 0x1000>;
0392 clocks = <&sspclk>, <&pclk>;
0393 clock-names = "sspclk", "apb_pclk";
0394 };
0395
0396 wdog0: watchdog@1000f000 {
0397 compatible = "arm,sp805", "arm,primecell";
0398 reg = <0x1000f000 0x1000>;
0399 clocks = <&wdogclk>, <&pclk>;
0400 clock-names = "wdog_clk", "apb_pclk";
0401 status = "disabled";
0402 };
0403
0404 wdog1: watchdog@10010000 {
0405 compatible = "arm,sp805", "arm,primecell";
0406 reg = <0x10010000 0x1000>;
0407 clocks = <&wdogclk>, <&pclk>;
0408 clock-names = "wdog_clk", "apb_pclk";
0409 status = "disabled";
0410 };
0411
0412 timer01: timer@10011000 {
0413 compatible = "arm,sp804", "arm,primecell";
0414 reg = <0x10011000 0x1000>;
0415 clocks = <&sp810_syscon0 0>,
0416 <&sp810_syscon0 1>,
0417 <&pclk>;
0418 clock-names = "timerclk0",
0419 "timerclk1",
0420 "apb_pclk";
0421 };
0422
0423 timer23: timer@10012000 {
0424 compatible = "arm,sp804", "arm,primecell";
0425 reg = <0x10012000 0x1000>;
0426 clocks = <&sp810_syscon0 2>,
0427 <&sp810_syscon0 3>,
0428 <&pclk>;
0429 clock-names = "timerclk2",
0430 "timerclk3",
0431 "apb_pclk";
0432 };
0433
0434 gpio0: gpio@10013000 {
0435 compatible = "arm,pl061", "arm,primecell";
0436 reg = <0x10013000 0x1000>;
0437 gpio-controller;
0438 #gpio-cells = <2>;
0439 interrupt-controller;
0440 #interrupt-cells = <2>;
0441 clocks = <&pclk>;
0442 clock-names = "apb_pclk";
0443 };
0444
0445 gpio1: gpio@10014000 {
0446 compatible = "arm,pl061", "arm,primecell";
0447 reg = <0x10014000 0x1000>;
0448 gpio-controller;
0449 #gpio-cells = <2>;
0450 interrupt-controller;
0451 #interrupt-cells = <2>;
0452 clocks = <&pclk>;
0453 clock-names = "apb_pclk";
0454 };
0455
0456 gpio2: gpio@10015000 {
0457 compatible = "arm,pl061", "arm,primecell";
0458 reg = <0x10015000 0x1000>;
0459 gpio-controller;
0460 #gpio-cells = <2>;
0461 interrupt-controller;
0462 #interrupt-cells = <2>;
0463 clocks = <&pclk>;
0464 clock-names = "apb_pclk";
0465 };
0466
0467 i2c1: i2c@10016000 {
0468 #address-cells = <1>;
0469 #size-cells = <0>;
0470 compatible = "arm,versatile-i2c";
0471 reg = <0x10016000 0x1000>;
0472 };
0473
0474 rtc: rtc@10017000 {
0475 compatible = "arm,pl031", "arm,primecell";
0476 reg = <0x10017000 0x1000>;
0477 clocks = <&pclk>;
0478 clock-names = "apb_pclk";
0479 };
0480
0481 timer45: timer@10018000 {
0482 compatible = "arm,sp804", "arm,primecell";
0483 reg = <0x10018000 0x1000>;
0484 clocks = <&timclk>, <&timclk>, <&pclk>;
0485 clock-names = "timerclk4", "timerclk5", "apb_pclk";
0486 };
0487
0488 timer67: timer@10019000 {
0489 compatible = "arm,sp804", "arm,primecell";
0490 reg = <0x10019000 0x1000>;
0491 clocks = <&timclk>, <&timclk>, <&pclk>;
0492 clock-names = "timerclk6", "timerclk7", "apb_pclk";
0493 };
0494
0495 sp810_syscon1: sysctl@1001a000 {
0496 compatible = "arm,sp810", "arm,primecell";
0497 reg = <0x1001a000 0x1000>;
0498 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
0499 clock-names = "refclk", "timclk", "apb_pclk";
0500 #clock-cells = <1>;
0501 clock-output-names = "timerclk4",
0502 "timerclk5",
0503 "timerclk6",
0504 "timerclk7";
0505 assigned-clocks = <&sp810_syscon1 0>,
0506 <&sp810_syscon1 1>,
0507 <&sp810_syscon1 2>,
0508 <&sp810_syscon1 3>;
0509 assigned-clock-parents = <&timclk>,
0510 <&timclk>,
0511 <&timclk>,
0512 <&timclk>;
0513 };
0514 };
0515
0516
0517 /* These peripherals are inside the FPGA */
0518 fpga {
0519 #address-cells = <1>;
0520 #size-cells = <1>;
0521 compatible = "simple-bus";
0522 ranges;
0523
0524 aaci: aaci@10004000 {
0525 compatible = "arm,pl041", "arm,primecell";
0526 reg = <0x10004000 0x1000>;
0527 clocks = <&pclk>;
0528 clock-names = "apb_pclk";
0529 };
0530
0531 mmc: mmcsd@10005000 {
0532 compatible = "arm,pl18x", "arm,primecell";
0533 reg = <0x10005000 0x1000>;
0534
0535 /* Due to frequent FIFO overruns, use just 500 kHz */
0536 max-frequency = <500000>;
0537 bus-width = <4>;
0538 cap-sd-highspeed;
0539 cap-mmc-highspeed;
0540 clocks = <&mclk>, <&pclk>;
0541 clock-names = "mclk", "apb_pclk";
0542 vmmc-supply = <&vmmc>;
0543 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
0544 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
0545 };
0546
0547 kmi0: kmi@10006000 {
0548 compatible = "arm,pl050", "arm,primecell";
0549 reg = <0x10006000 0x1000>;
0550 clocks = <&kmiclk>, <&pclk>;
0551 clock-names = "KMIREFCLK", "apb_pclk";
0552 };
0553
0554 kmi1: kmi@10007000 {
0555 compatible = "arm,pl050", "arm,primecell";
0556 reg = <0x10007000 0x1000>;
0557 clocks = <&kmiclk>, <&pclk>;
0558 clock-names = "KMIREFCLK", "apb_pclk";
0559 };
0560
0561 serial3: serial@1000c000 {
0562 compatible = "arm,pl011", "arm,primecell";
0563 reg = <0x1000c000 0x1000>;
0564 clocks = <&uartclk>, <&pclk>;
0565 clock-names = "uartclk", "apb_pclk";
0566 };
0567 };
0568
0569 /* These peripherals are inside the NEC ISSP */
0570 issp {
0571 #address-cells = <1>;
0572 #size-cells = <1>;
0573 compatible = "simple-bus";
0574 ranges;
0575
0576 clcd: clcd@10020000 {
0577 compatible = "arm,pl111", "arm,primecell";
0578 reg = <0x10020000 0x1000>;
0579 interrupt-names = "combined";
0580 clocks = <&oscclk4>, <&pclk>;
0581 clock-names = "clcdclk", "apb_pclk";
0582 /* 1024x768 16bpp @65MHz works fine */
0583 max-memory-bandwidth = <95000000>;
0584
0585 port {
0586 clcd_pads: endpoint {
0587 remote-endpoint = <&vga_bridge_in>;
0588 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
0589 };
0590 };
0591 };
0592 };
0593 };
