0001 /*
0002 * Copyright 2016 Linaro Ltd
0003 *
0004 * Permission is hereby granted, free of charge, to any person obtaining a copy
0005 * of this software and associated documentation files (the "Software"), to deal
0006 * in the Software without restriction, including without limitation the rights
0007 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
0008 * copies of the Software, and to permit persons to whom the Software is
0009 * furnished to do so, subject to the following conditions:
0010 *
0011 * The above copyright notice and this permission notice shall be included in
0012 * all copies or substantial portions of the Software.
0013 *
0014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
0017 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0019 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
0020 * THE SOFTWARE.
0021 */
0022
0023 /dts-v1/;
0024 #include "arm-realview-pbx.dtsi"
0025
0026 / {
0027 /*
0028 * This is the RealView Platform Baseboard Explore for Cortex-A9
0029 * (HBI0182 + HBI0183) as described in ARM DUI 0440B
0030 */
0031 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
0032 arm,hbi = <0x182>;
0033
0034 cpus {
0035 #address-cells = <1>;
0036 #size-cells = <0>;
0037 enable-method = "arm,realview-smp";
0038
0039 cpu-map {
0040 cluster0 {
0041 core0 {
0042 cpu = <&CPU0>;
0043 };
0044 core1 {
0045 cpu = <&CPU1>;
0046 };
0047 };
0048 };
0049 CPU0: cpu@0 {
0050 device_type = "cpu";
0051 compatible = "arm,cortex-a9";
0052 reg = <0x0>;
0053 next-level-cache = <&L2>;
0054 };
0055 CPU1: cpu@1 {
0056 device_type = "cpu";
0057 compatible = "arm,cortex-a9";
0058 reg = <0x1>;
0059 next-level-cache = <&L2>;
0060 };
0061 };
0062
0063 L2: cache-controller {
0064 compatible = "arm,pl310-cache";
0065 reg = <0x1f002000 0x1000>;
0066 cache-unified;
0067 cache-level = <2>;
0068 /*
0069 * Override default cache size, sets and
0070 * associativity as these may be erroneously set
0071 * up by boot loader(s).
0072 */
0073 cache-size = <131072>; // 128KB
0074 cache-sets = <512>;
0075 cache-line-size = <32>;
0076 arm,parity-disable;
0077 arm,tag-latency = <1 1 1>;
0078 arm,data-latency = <1 1 1>;
0079 };
0080
0081 scu: scu@1f000000 {
0082 compatible = "arm,cortex-a9-scu";
0083 reg = <0x1f000000 0x100>;
0084 };
0085
0086 twd_timer: timer@1f000600 {
0087 compatible = "arm,cortex-a9-twd-timer";
0088 reg = <0x1f000600 0x20>;
0089 interrupt-parent = <&intc>;
0090 interrupts = <1 13 0xf04>;
0091 };
0092
0093 twd_wdog: watchdog@1f000620 {
0094 compatible = "arm,cortex-a9-twd-wdt";
0095 reg = <0x1f000620 0x20>;
0096 interrupt-parent = <&intc>;
0097 interrupts = <1 14 0xf04>;
0098 };
0099
0100 pmu: pmu@0 {
0101 compatible = "arm,cortex-a9-pmu";
0102 interrupt-parent = <&intc>;
0103 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>,
0104 <0 45 IRQ_TYPE_LEVEL_HIGH>;
0105 interrupt-affinity = <&CPU0>, <&CPU1>;
0106 };
0107
0108 /* Primary GIC PL390 interrupt controller in the test chip */
0109 intc: interrupt-controller@1f000000 {
0110 compatible = "arm,cortex-a9-gic";
0111 #interrupt-cells = <3>;
0112 #address-cells = <1>;
0113 interrupt-controller;
0114 reg = <0x1f001000 0x1000>,
0115 <0x1f000100 0x100>;
0116 };
0117 };
0118
0119 ðernet {
0120 interrupt-parent = <&intc>;
0121 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
0122 };
0123
0124 &usb {
0125 interrupt-parent = <&intc>;
0126 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
0127 };
0128
0129 &serial0 {
0130 interrupt-parent = <&intc>;
0131 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
0132 };
0133
0134 &serial1 {
0135 interrupt-parent = <&intc>;
0136 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
0137 };
0138
0139 &serial2 {
0140 interrupt-parent = <&intc>;
0141 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
0142 };
0143
0144 &serial3 {
0145 interrupt-parent = <&intc>;
0146 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
0147 };
0148
0149 &ssp {
0150 interrupt-parent = <&intc>;
0151 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
0152 };
0153
0154 &wdog0 {
0155 interrupt-parent = <&intc>;
0156 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
0157 };
0158
0159 &wdog1 {
0160 interrupt-parent = <&intc>;
0161 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
0162 };
0163
0164 &timer01 {
0165 interrupt-parent = <&intc>;
0166 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
0167 };
0168
0169 &timer23 {
0170 interrupt-parent = <&intc>;
0171 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
0172 };
0173
0174 &gpio0 {
0175 interrupt-parent = <&intc>;
0176 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
0177 };
0178
0179 &gpio1 {
0180 interrupt-parent = <&intc>;
0181 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
0182 };
0183
0184 &gpio2 {
0185 interrupt-parent = <&intc>;
0186 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
0187 };
0188
0189 &rtc {
0190 interrupt-parent = <&intc>;
0191 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
0192 };
0193
0194 &timer45 {
0195 interrupt-parent = <&intc>;
0196 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
0197 };
0198
0199 &timer67 {
0200 interrupt-parent = <&intc>;
0201 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
0202 };
0203
0204 &aaci {
0205 interrupt-parent = <&intc>;
0206 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
0207 };
0208
0209 &mmc {
0210 interrupt-parent = <&intc>;
0211 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
0212 <0 18 IRQ_TYPE_LEVEL_HIGH>;
0213 };
0214
0215 &kmi0 {
0216 interrupt-parent = <&intc>;
0217 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
0218 };
0219
0220 &kmi1 {
0221 interrupt-parent = <&intc>;
0222 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
0223 };
0224
0225 &clcd {
0226 interrupt-parent = <&intc>;
0227 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
0228 };
