0001 /*
0002 * Copyright 2015 Linaro Ltd
0003 *
0004 * Permission is hereby granted, free of charge, to any person obtaining a copy
0005 * of this software and associated documentation files (the "Software"), to deal
0006 * in the Software without restriction, including without limitation the rights
0007 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
0008 * copies of the Software, and to permit persons to whom the Software is
0009 * furnished to do so, subject to the following conditions:
0010 *
0011 * The above copyright notice and this permission notice shall be included in
0012 * all copies or substantial portions of the Software.
0013 *
0014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
0017 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0019 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
0020 * THE SOFTWARE.
0021 */
0022
0023 /dts-v1/;
0024 #include <dt-bindings/interrupt-controller/irq.h>
0025 #include <dt-bindings/gpio/gpio.h>
0026
0027 / {
0028 #address-cells = <1>;
0029 #size-cells = <1>;
0030 model = "ARM RealView PB11MPcore";
0031 compatible = "arm,realview-pb11mp";
0032
0033 chosen { };
0034
0035 aliases {
0036 serial0 = &pb11mp_serial0;
0037 serial1 = &pb11mp_serial1;
0038 serial2 = &pb11mp_serial2;
0039 serial3 = &pb11mp_serial3;
0040 };
0041
0042 memory {
0043 device_type = "memory";
0044 /*
0045 * The PB11MPCore has 512 MiB memory @ 0x70000000
0046 * and the first 256 are also remapped @ 0x00000000
0047 */
0048 reg = <0x70000000 0x20000000>;
0049 };
0050
0051 cpus {
0052 #address-cells = <1>;
0053 #size-cells = <0>;
0054 enable-method = "arm,realview-smp";
0055
0056 MP11_0: cpu@0 {
0057 device_type = "cpu";
0058 compatible = "arm,arm11mpcore";
0059 reg = <0>;
0060 next-level-cache = <&L2>;
0061 };
0062
0063 MP11_1: cpu@1 {
0064 device_type = "cpu";
0065 compatible = "arm,arm11mpcore";
0066 reg = <1>;
0067 next-level-cache = <&L2>;
0068 };
0069
0070 MP11_2: cpu@2 {
0071 device_type = "cpu";
0072 compatible = "arm,arm11mpcore";
0073 reg = <2>;
0074 next-level-cache = <&L2>;
0075 };
0076
0077 MP11_3: cpu@3 {
0078 device_type = "cpu";
0079 compatible = "arm,arm11mpcore";
0080 reg = <3>;
0081 next-level-cache = <&L2>;
0082 };
0083 };
0084
0085 /* Primary TestChip GIC synthesized with the CPU */
0086 intc_tc11mp: interrupt-controller@1f000100 {
0087 compatible = "arm,tc11mp-gic";
0088 #interrupt-cells = <3>;
0089 #address-cells = <1>;
0090 interrupt-controller;
0091 reg = <0x1f001000 0x1000>,
0092 <0x1f000100 0x100>;
0093 };
0094
0095 L2: cache-controller {
0096 compatible = "arm,l220-cache";
0097 reg = <0x1f002000 0x1000>;
0098 interrupt-parent = <&intc_tc11mp>;
0099 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
0100 <0 30 IRQ_TYPE_LEVEL_HIGH>,
0101 <0 31 IRQ_TYPE_LEVEL_HIGH>;
0102 cache-unified;
0103 cache-level = <2>;
0104 /*
0105 * Override default cache size, sets and
0106 * associativity as these may be erroneously set
0107 * up by boot loader(s), probably for safety
0108 * since th outer sync operation can cause the
0109 * cache to hang unless disabled.
0110 */
0111 cache-size = <1048576>; // 1MB
0112 cache-sets = <4096>;
0113 cache-line-size = <32>;
0114 arm,shared-override;
0115 arm,parity-enable;
0116 arm,outer-sync-disable;
0117 };
0118
0119 scu@1f000000 {
0120 compatible = "arm,arm11mp-scu";
0121 reg = <0x1f000000 0x100>;
0122 };
0123
0124 timer@1f000600 {
0125 compatible = "arm,arm11mp-twd-timer";
0126 reg = <0x1f000600 0x20>;
0127 interrupt-parent = <&intc_tc11mp>;
0128 interrupts = <1 13 0xf04>;
0129 };
0130
0131 watchdog@1f000620 {
0132 compatible = "arm,arm11mp-twd-wdt";
0133 reg = <0x1f000620 0x20>;
0134 interrupt-parent = <&intc_tc11mp>;
0135 interrupts = <1 14 0xf04>;
0136 };
0137
0138 /* PMU with one IRQ line per core */
0139 pmu {
0140 compatible = "arm,arm11mpcore-pmu";
0141 interrupt-parent = <&intc_tc11mp>;
0142 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
0143 <0 18 IRQ_TYPE_LEVEL_HIGH>,
0144 <0 19 IRQ_TYPE_LEVEL_HIGH>,
0145 <0 20 IRQ_TYPE_LEVEL_HIGH>;
0146 interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
0147 };
0148
0149 /* The voltage to the MMC card is hardwired at 3.3V */
0150 vmmc: regulator-vmmc {
0151 compatible = "regulator-fixed";
0152 regulator-name = "vmmc";
0153 regulator-min-microvolt = <3300000>;
0154 regulator-max-microvolt = <3300000>;
0155 regulator-boot-on;
0156 };
0157
0158 veth: regulator-veth {
0159 compatible = "regulator-fixed";
0160 regulator-name = "veth";
0161 regulator-min-microvolt = <3300000>;
0162 regulator-max-microvolt = <3300000>;
0163 regulator-boot-on;
0164 };
0165
0166 xtal24mhz: xtal24mhz@24M {
0167 #clock-cells = <0>;
0168 compatible = "fixed-clock";
0169 clock-frequency = <24000000>;
0170 };
0171
0172 refclk32khz: refclk32khz {
0173 compatible = "fixed-clock";
0174 #clock-cells = <0>;
0175 clock-frequency = <32768>;
0176 };
0177
0178 timclk: timclk@1M {
0179 #clock-cells = <0>;
0180 compatible = "fixed-factor-clock";
0181 clock-div = <24>;
0182 clock-mult = <1>;
0183 clocks = <&xtal24mhz>;
0184 };
0185
0186 mclk: mclk@24M {
0187 #clock-cells = <0>;
0188 compatible = "fixed-factor-clock";
0189 clock-div = <1>;
0190 clock-mult = <1>;
0191 clocks = <&xtal24mhz>;
0192 };
0193
0194 kmiclk: kmiclk@24M {
0195 #clock-cells = <0>;
0196 compatible = "fixed-factor-clock";
0197 clock-div = <1>;
0198 clock-mult = <1>;
0199 clocks = <&xtal24mhz>;
0200 };
0201
0202 sspclk: sspclk@24M {
0203 #clock-cells = <0>;
0204 compatible = "fixed-factor-clock";
0205 clock-div = <1>;
0206 clock-mult = <1>;
0207 clocks = <&xtal24mhz>;
0208 };
0209
0210 uartclk: uartclk@24M {
0211 #clock-cells = <0>;
0212 compatible = "fixed-factor-clock";
0213 clock-div = <1>;
0214 clock-mult = <1>;
0215 clocks = <&xtal24mhz>;
0216 };
0217
0218 wdogclk: wdogclk@24M {
0219 #clock-cells = <0>;
0220 compatible = "fixed-factor-clock";
0221 clock-div = <1>;
0222 clock-mult = <1>;
0223 clocks = <&xtal24mhz>;
0224 };
0225
0226 /* FIXME: this actually hangs off the PLL clocks */
0227 pclk: pclk@0 {
0228 #clock-cells = <0>;
0229 compatible = "fixed-clock";
0230 clock-frequency = <0>;
0231 };
0232
0233 flash0@40000000 {
0234 /* 2 * 32MiB NOR Flash memory */
0235 compatible = "arm,versatile-flash", "cfi-flash";
0236 reg = <0x40000000 0x04000000>;
0237 bank-width = <4>;
0238 partitions {
0239 compatible = "arm,arm-firmware-suite";
0240 };
0241 };
0242
0243 flash1@44000000 {
0244 // 2 * 32MiB NOR Flash memory
0245 compatible = "arm,versatile-flash", "cfi-flash";
0246 reg = <0x44000000 0x04000000>;
0247 bank-width = <4>;
0248 partitions {
0249 compatible = "arm,arm-firmware-suite";
0250 };
0251 };
0252
0253 bridge {
0254 compatible = "ti,ths8134a", "ti,ths8134";
0255 #address-cells = <1>;
0256 #size-cells = <0>;
0257
0258 ports {
0259 #address-cells = <1>;
0260 #size-cells = <0>;
0261
0262 port@0 {
0263 reg = <0>;
0264
0265 vga_bridge_in: endpoint {
0266 remote-endpoint = <&clcd_pads>;
0267 };
0268 };
0269
0270 port@1 {
0271 reg = <1>;
0272
0273 vga_bridge_out: endpoint {
0274 remote-endpoint = <&vga_con_in>;
0275 };
0276 };
0277 };
0278 };
0279
0280 vga {
0281 /*
0282 * This DDC I2C is connected directly to the DVI portions
0283 * of the connector, so it's not really working when the
0284 * monitor is connected to the VGA connector.
0285 */
0286 compatible = "vga-connector";
0287 ddc-i2c-bus = <&i2c1>;
0288
0289 port {
0290 vga_con_in: endpoint {
0291 remote-endpoint = <&vga_bridge_out>;
0292 };
0293 };
0294 };
0295
0296 soc {
0297 #address-cells = <1>;
0298 #size-cells = <1>;
0299 compatible = "arm,realview-pb11mp-soc", "simple-bus";
0300 regmap = <&pb11mp_syscon>;
0301 ranges;
0302
0303 pb11mp_syscon: syscon@10000000 {
0304 compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
0305 reg = <0x10000000 0x1000>;
0306 ranges = <0x0 0x10000000 0x1000>;
0307 #address-cells = <1>;
0308 #size-cells = <1>;
0309
0310 led@8,0 {
0311 compatible = "register-bit-led";
0312 reg = <0x08 0x04>;
0313 offset = <0x08>;
0314 mask = <0x01>;
0315 label = "versatile:0";
0316 linux,default-trigger = "heartbeat";
0317 default-state = "on";
0318 };
0319 led@8,1 {
0320 compatible = "register-bit-led";
0321 reg = <0x08 0x04>;
0322 offset = <0x08>;
0323 mask = <0x02>;
0324 label = "versatile:1";
0325 linux,default-trigger = "mmc0";
0326 default-state = "off";
0327 };
0328 led@8,2 {
0329 compatible = "register-bit-led";
0330 reg = <0x08 0x04>;
0331 offset = <0x08>;
0332 mask = <0x04>;
0333 label = "versatile:2";
0334 linux,default-trigger = "cpu0";
0335 default-state = "off";
0336 };
0337 led@8,3 {
0338 compatible = "register-bit-led";
0339 reg = <0x08 0x04>;
0340 offset = <0x08>;
0341 mask = <0x08>;
0342 label = "versatile:3";
0343 linux,default-trigger = "cpu1";
0344 default-state = "off";
0345 };
0346 led@8,4 {
0347 compatible = "register-bit-led";
0348 reg = <0x08 0x04>;
0349 offset = <0x08>;
0350 mask = <0x10>;
0351 label = "versatile:4";
0352 linux,default-trigger = "cpu2";
0353 default-state = "off";
0354 };
0355 led@8,5 {
0356 compatible = "register-bit-led";
0357 reg = <0x08 0x04>;
0358 offset = <0x08>;
0359 mask = <0x20>;
0360 label = "versatile:5";
0361 linux,default-trigger = "cpu3";
0362 default-state = "off";
0363 };
0364 led@8,6 {
0365 compatible = "register-bit-led";
0366 reg = <0x08 0x04>;
0367 offset = <0x08>;
0368 mask = <0x40>;
0369 label = "versatile:6";
0370 default-state = "off";
0371 };
0372 led@8,7 {
0373 compatible = "register-bit-led";
0374 reg = <0x08 0x04>;
0375 offset = <0x08>;
0376 mask = <0x80>;
0377 label = "versatile:7";
0378 default-state = "off";
0379 };
0380
0381 oscclk0: clock-controller@c {
0382 compatible = "arm,syscon-icst307";
0383 reg = <0x0c 0x04>;
0384 #clock-cells = <0>;
0385 lock-offset = <0x20>;
0386 vco-offset = <0x0C>;
0387 clocks = <&xtal24mhz>;
0388 };
0389 oscclk1: clock-controller@10 {
0390 compatible = "arm,syscon-icst307";
0391 reg = <0x10 0x04>;
0392 #clock-cells = <0>;
0393 lock-offset = <0x20>;
0394 vco-offset = <0x10>;
0395 clocks = <&xtal24mhz>;
0396 };
0397 oscclk2: clock-controller@14 {
0398 compatible = "arm,syscon-icst307";
0399 reg = <0x14 0x04>;
0400 #clock-cells = <0>;
0401 lock-offset = <0x20>;
0402 vco-offset = <0x14>;
0403 clocks = <&xtal24mhz>;
0404 };
0405 oscclk3: clock-controller@18 {
0406 compatible = "arm,syscon-icst307";
0407 reg = <0x18 0x04>;
0408 #clock-cells = <0>;
0409 lock-offset = <0x20>;
0410 vco-offset = <0x18>;
0411 clocks = <&xtal24mhz>;
0412 };
0413 oscclk4: clock-controller@1c {
0414 compatible = "arm,syscon-icst307";
0415 reg = <0x1c 0x04>;
0416 #clock-cells = <0>;
0417 lock-offset = <0x20>;
0418 vco-offset = <0x1c>;
0419 clocks = <&xtal24mhz>;
0420 };
0421 oscclk5: clock-controller@d4 {
0422 compatible = "arm,syscon-icst307";
0423 reg = <0xd4 0x04>;
0424 #clock-cells = <0>;
0425 lock-offset = <0x20>;
0426 vco-offset = <0xd4>;
0427 clocks = <&xtal24mhz>;
0428 };
0429 oscclk6: clock-controller@d8 {
0430 compatible = "arm,syscon-icst307";
0431 reg = <0xd8 0x04>;
0432 #clock-cells = <0>;
0433 lock-offset = <0x20>;
0434 vco-offset = <0xd8>;
0435 clocks = <&xtal24mhz>;
0436 };
0437 };
0438
0439 sp810_syscon: sysctl@10001000 {
0440 compatible = "arm,sp810", "arm,primecell";
0441 reg = <0x10001000 0x1000>;
0442 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
0443 clock-names = "refclk", "timclk", "apb_pclk";
0444 #clock-cells = <1>;
0445 clock-output-names = "timerclk0",
0446 "timerclk1",
0447 "timerclk2",
0448 "timerclk3";
0449 assigned-clocks = <&sp810_syscon 0>,
0450 <&sp810_syscon 1>,
0451 <&sp810_syscon 2>,
0452 <&sp810_syscon 3>;
0453 assigned-clock-parents = <&timclk>,
0454 <&timclk>,
0455 <&timclk>,
0456 <&timclk>;
0457 };
0458
0459 i2c0: i2c@10002000 {
0460 #address-cells = <1>;
0461 #size-cells = <0>;
0462 compatible = "arm,versatile-i2c";
0463 reg = <0x10002000 0x1000>;
0464
0465 rtc@68 {
0466 compatible = "dallas,ds1338";
0467 reg = <0x68>;
0468 };
0469 };
0470
0471 aaci: aaci@10004000 {
0472 compatible = "arm,pl041", "arm,primecell";
0473 reg = <0x10004000 0x1000>;
0474 interrupt-parent = <&intc_tc11mp>;
0475 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
0476 clocks = <&pclk>;
0477 clock-names = "apb_pclk";
0478 };
0479
0480 mci: mmcsd@10005000 {
0481 compatible = "arm,pl18x", "arm,primecell";
0482 reg = <0x10005000 0x1000>;
0483 interrupt-parent = <&intc_tc11mp>;
0484 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
0485 <0 15 IRQ_TYPE_LEVEL_HIGH>;
0486 /* Due to frequent FIFO overruns, use just 500 kHz */
0487 max-frequency = <500000>;
0488 bus-width = <4>;
0489 cap-sd-highspeed;
0490 cap-mmc-highspeed;
0491 clocks = <&mclk>, <&pclk>;
0492 clock-names = "mclk", "apb_pclk";
0493 vmmc-supply = <&vmmc>;
0494 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
0495 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
0496 };
0497
0498 kmi0: kmi@10006000 {
0499 compatible = "arm,pl050", "arm,primecell";
0500 reg = <0x10006000 0x1000>;
0501 interrupt-parent = <&intc_tc11mp>;
0502 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
0503 clocks = <&kmiclk>, <&pclk>;
0504 clock-names = "KMIREFCLK", "apb_pclk";
0505 };
0506
0507 kmi1: kmi@10007000 {
0508 compatible = "arm,pl050", "arm,primecell";
0509 reg = <0x10007000 0x1000>;
0510 interrupt-parent = <&intc_tc11mp>;
0511 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
0512 clocks = <&kmiclk>, <&pclk>;
0513 clock-names = "KMIREFCLK", "apb_pclk";
0514 };
0515
0516 pb11mp_serial0: serial@10009000 {
0517 compatible = "arm,pl011", "arm,primecell";
0518 reg = <0x10009000 0x1000>;
0519 interrupt-parent = <&intc_tc11mp>;
0520 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
0521 clocks = <&uartclk>, <&pclk>;
0522 clock-names = "uartclk", "apb_pclk";
0523 };
0524
0525 pb11mp_serial1: serial@1000a000 {
0526 compatible = "arm,pl011", "arm,primecell";
0527 reg = <0x1000a000 0x1000>;
0528 interrupt-parent = <&intc_tc11mp>;
0529 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
0530 clocks = <&uartclk>, <&pclk>;
0531 clock-names = "uartclk", "apb_pclk";
0532 };
0533
0534 pb11mp_serial2: serial@1000b000 {
0535 compatible = "arm,pl011", "arm,primecell";
0536 reg = <0x1000b000 0x1000>;
0537 interrupt-parent = <&intc_pb11mp>;
0538 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
0539 clocks = <&uartclk>, <&pclk>;
0540 clock-names = "uartclk", "apb_pclk";
0541 };
0542
0543 pb11mp_serial3: serial@1000c000 {
0544 compatible = "arm,pl011", "arm,primecell";
0545 reg = <0x1000c000 0x1000>;
0546 interrupt-parent = <&intc_pb11mp>;
0547 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
0548 clocks = <&uartclk>, <&pclk>;
0549 clock-names = "uartclk", "apb_pclk";
0550 };
0551
0552 spi@1000d000 {
0553 compatible = "arm,pl022", "arm,primecell";
0554 reg = <0x1000d000 0x1000>;
0555 interrupt-parent = <&intc_pb11mp>;
0556 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
0557 clocks = <&sspclk>, <&pclk>;
0558 clock-names = "sspclk", "apb_pclk";
0559 };
0560
0561 watchdog@1000f000 {
0562 compatible = "arm,sp805", "arm,primecell";
0563 reg = <0x1000f000 0x1000>;
0564 interrupt-parent = <&intc_pb11mp>;
0565 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
0566 clocks = <&wdogclk>, <&pclk>;
0567 clock-names = "wdog_clk", "apb_pclk";
0568 status = "disabled";
0569 };
0570
0571 watchdog@10010000 {
0572 compatible = "arm,sp805", "arm,primecell";
0573 reg = <0x10010000 0x1000>;
0574 interrupt-parent = <&intc_pb11mp>;
0575 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
0576 clocks = <&wdogclk>, <&pclk>;
0577 clock-names = "wdog_clk", "apb_pclk";
0578 };
0579
0580 timer01: timer@10011000 {
0581 compatible = "arm,sp804", "arm,primecell";
0582 reg = <0x10011000 0x1000>;
0583 interrupt-parent = <&intc_tc11mp>;
0584 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
0585 arm,sp804-has-irq = <1>;
0586 clocks = <&sp810_syscon 0>,
0587 <&sp810_syscon 1>,
0588 <&pclk>;
0589 clock-names = "timer0clk",
0590 "timer1clk",
0591 "apb_pclk";
0592 };
0593
0594 timer23: timer@10012000 {
0595 compatible = "arm,sp804", "arm,primecell";
0596 reg = <0x10012000 0x1000>;
0597 interrupt-parent = <&intc_tc11mp>;
0598 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
0599 arm,sp804-has-irq = <1>;
0600 clocks = <&sp810_syscon 2>,
0601 <&sp810_syscon 3>,
0602 <&pclk>;
0603 clock-names = "timer0clk",
0604 "timer1clk",
0605 "apb_pclk";
0606 };
0607
0608 gpio0: gpio@10013000 {
0609 compatible = "arm,pl061", "arm,primecell";
0610 reg = <0x10013000 0x1000>;
0611 gpio-controller;
0612 interrupt-parent = <&intc_pb11mp>;
0613 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
0614 #gpio-cells = <2>;
0615 interrupt-controller;
0616 #interrupt-cells = <2>;
0617 clocks = <&pclk>;
0618 clock-names = "apb_pclk";
0619 };
0620
0621 gpio1: gpio@10014000 {
0622 compatible = "arm,pl061", "arm,primecell";
0623 reg = <0x10014000 0x1000>;
0624 gpio-controller;
0625 interrupt-parent = <&intc_pb11mp>;
0626 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
0627 #gpio-cells = <2>;
0628 interrupt-controller;
0629 #interrupt-cells = <2>;
0630 clocks = <&pclk>;
0631 clock-names = "apb_pclk";
0632 };
0633
0634 gpio2: gpio@10015000 {
0635 compatible = "arm,pl061", "arm,primecell";
0636 reg = <0x10015000 0x1000>;
0637 gpio-controller;
0638 interrupt-parent = <&intc_pb11mp>;
0639 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
0640 #gpio-cells = <2>;
0641 interrupt-controller;
0642 #interrupt-cells = <2>;
0643 clocks = <&pclk>;
0644 clock-names = "apb_pclk";
0645 };
0646
0647 i2c1: i2c@10016000 {
0648 #address-cells = <1>;
0649 #size-cells = <0>;
0650 compatible = "arm,versatile-i2c";
0651 reg = <0x10016000 0x1000>;
0652 };
0653
0654 rtc: rtc@10017000 {
0655 compatible = "arm,pl031", "arm,primecell";
0656 reg = <0x10017000 0x1000>;
0657 interrupt-parent = <&intc_tc11mp>;
0658 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
0659 clocks = <&pclk>;
0660 clock-names = "apb_pclk";
0661 };
0662
0663 timer45: timer@10018000 {
0664 compatible = "arm,sp804", "arm,primecell";
0665 reg = <0x10018000 0x1000>;
0666 clocks = <&timclk>, <&timclk>, <&pclk>;
0667 clock-names = "timer0clk", "timer1clk", "apb_pclk";
0668 status = "disabled";
0669 };
0670
0671 timer67: timer@10019000 {
0672 compatible = "arm,sp804", "arm,primecell";
0673 reg = <0x10019000 0x1000>;
0674 clocks = <&timclk>, <&timclk>, <&pclk>;
0675 clock-names = "timer0clk", "timer1clk", "apb_pclk";
0676 status = "disabled";
0677 };
0678
0679
0680 clcd@10020000 {
0681 compatible = "arm,pl111", "arm,primecell";
0682 reg = <0x10020000 0x1000>;
0683 interrupt-parent = <&intc_pb11mp>;
0684 interrupt-names = "combined";
0685 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
0686 clocks = <&oscclk4>, <&pclk>;
0687 clock-names = "clcdclk", "apb_pclk";
0688 /* 1024x768 16bpp @65MHz works fine */
0689 max-memory-bandwidth = <95000000>;
0690
0691 port {
0692 clcd_pads: endpoint {
0693 remote-endpoint = <&vga_bridge_in>;
0694 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
0695 };
0696 };
0697 };
0698
0699 /*
0700 * This GIC on the Platform Baseboard is cascaded off the
0701 * TestChip GIC
0702 */
0703 intc_pb11mp: interrupt-controller@1e000000 {
0704 compatible = "arm,arm11mp-gic";
0705 #interrupt-cells = <3>;
0706 #address-cells = <1>;
0707 interrupt-controller;
0708 reg = <0x1e001000 0x1000>,
0709 <0x1e000000 0x100>;
0710 interrupt-parent = <&intc_tc11mp>;
0711 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
0712 };
0713
0714 /* SMSC 9118 ethernet with PHY and EEPROM */
0715 ethernet@4e000000 {
0716 compatible = "smsc,lan9118", "smsc,lan9115";
0717 reg = <0x4e000000 0x10000>;
0718 interrupt-parent = <&intc_tc11mp>;
0719 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
0720 phy-mode = "mii";
0721 reg-io-width = <4>;
0722 smsc,irq-active-high;
0723 smsc,irq-push-pull;
0724 vdd33a-supply = <&veth>;
0725 vddvario-supply = <&veth>;
0726 };
0727
0728 usb@4f000000 {
0729 compatible = "nxp,usb-isp1761";
0730 reg = <0x4f000000 0x20000>;
0731 interrupt-parent = <&intc_tc11mp>;
0732 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
0733 dr_mode = "peripheral";
0734 };
0735 };
0736 };
