0001 /*
0002 * Copyright 2014 Linaro Ltd
0003 *
0004 * Permission is hereby granted, free of charge, to any person obtaining a copy
0005 * of this software and associated documentation files (the "Software"), to deal
0006 * in the Software without restriction, including without limitation the rights
0007 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
0008 * copies of the Software, and to permit persons to whom the Software is
0009 * furnished to do so, subject to the following conditions:
0010 *
0011 * The above copyright notice and this permission notice shall be included in
0012 * all copies or substantial portions of the Software.
0013 *
0014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
0017 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0019 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
0020 * THE SOFTWARE.
0021 */
0022
0023 /dts-v1/;
0024 #include <dt-bindings/interrupt-controller/irq.h>
0025 #include <dt-bindings/gpio/gpio.h>
0026
0027 / {
0028 #address-cells = <1>;
0029 #size-cells = <1>;
0030 model = "ARM RealView PB1176";
0031 compatible = "arm,realview-pb1176";
0032
0033 chosen { };
0034
0035 aliases {
0036 serial0 = &pb1176_serial0;
0037 serial1 = &pb1176_serial1;
0038 serial2 = &pb1176_serial2;
0039 serial3 = &pb1176_serial3;
0040 serial4 = &fpga_serial;
0041 };
0042
0043 memory {
0044 device_type = "memory";
0045 /* 128 MiB memory @ 0x0 */
0046 reg = <0x00000000 0x08000000>;
0047 };
0048
0049 /* The voltage to the MMC card is hardwired at 3.3V */
0050 vmmc: regulator-vmmc {
0051 compatible = "regulator-fixed";
0052 regulator-name = "vmmc";
0053 regulator-min-microvolt = <3300000>;
0054 regulator-max-microvolt = <3300000>;
0055 regulator-boot-on;
0056 };
0057
0058 veth: regulator-veth {
0059 compatible = "regulator-fixed";
0060 regulator-name = "veth";
0061 regulator-min-microvolt = <3300000>;
0062 regulator-max-microvolt = <3300000>;
0063 regulator-boot-on;
0064 };
0065
0066 xtal24mhz: xtal24mhz@24M {
0067 #clock-cells = <0>;
0068 compatible = "fixed-clock";
0069 clock-frequency = <24000000>;
0070 };
0071
0072 timclk: timclk@1M {
0073 #clock-cells = <0>;
0074 compatible = "fixed-factor-clock";
0075 clock-div = <24>;
0076 clock-mult = <1>;
0077 clocks = <&xtal24mhz>;
0078 };
0079
0080 mclk: mclk@24M {
0081 #clock-cells = <0>;
0082 compatible = "fixed-factor-clock";
0083 clock-div = <1>;
0084 clock-mult = <1>;
0085 clocks = <&xtal24mhz>;
0086 };
0087
0088 kmiclk: kmiclk@24M {
0089 #clock-cells = <0>;
0090 compatible = "fixed-factor-clock";
0091 clock-div = <1>;
0092 clock-mult = <1>;
0093 clocks = <&xtal24mhz>;
0094 };
0095
0096 sspclk: sspclk@24M {
0097 #clock-cells = <0>;
0098 compatible = "fixed-factor-clock";
0099 clock-div = <1>;
0100 clock-mult = <1>;
0101 clocks = <&xtal24mhz>;
0102 };
0103
0104 uartclk: uartclk@24M {
0105 #clock-cells = <0>;
0106 compatible = "fixed-factor-clock";
0107 clock-div = <1>;
0108 clock-mult = <1>;
0109 clocks = <&xtal24mhz>;
0110 };
0111
0112 /* FIXME: this actually hangs off the PLL clocks */
0113 pclk: pclk@0 {
0114 #clock-cells = <0>;
0115 compatible = "fixed-clock";
0116 clock-frequency = <0>;
0117 };
0118
0119 flash@30000000 {
0120 compatible = "arm,versatile-flash", "cfi-flash";
0121 reg = <0x30000000 0x4000000>;
0122 bank-width = <4>;
0123 partitions {
0124 compatible = "arm,arm-firmware-suite";
0125 };
0126 };
0127
0128 fpga_flash@38000000 {
0129 compatible = "arm,versatile-flash", "cfi-flash";
0130 reg = <0x38000000 0x800000>;
0131 bank-width = <4>;
0132 partitions {
0133 compatible = "arm,arm-firmware-suite";
0134 };
0135 };
0136
0137 /*
0138 * The "secure flash" contains things like the boot
0139 * monitor so we don't want people to accidentally
0140 * screw this up. Mark the device tree node disabled
0141 * by default.
0142 */
0143 secflash@3c000000 {
0144 compatible = "arm,versatile-flash", "cfi-flash";
0145 reg = <0x3c000000 0x4000000>;
0146 bank-width = <4>;
0147 status = "disabled";
0148 };
0149
0150 /* SMSC 9118 ethernet with PHY and EEPROM */
0151 ethernet@3a000000 {
0152 compatible = "smsc,lan9118", "smsc,lan9115";
0153 reg = <0x3a000000 0x10000>;
0154 interrupt-parent = <&intc_fpga1176>;
0155 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
0156 phy-mode = "mii";
0157 reg-io-width = <4>;
0158 smsc,irq-active-high;
0159 smsc,irq-push-pull;
0160 vdd33a-supply = <&veth>;
0161 vddvario-supply = <&veth>;
0162 };
0163
0164 usb@3b000000 {
0165 compatible = "nxp,usb-isp1761";
0166 reg = <0x3b000000 0x20000>;
0167 interrupt-parent = <&intc_fpga1176>;
0168 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
0169 dr_mode = "peripheral";
0170 };
0171
0172 bridge {
0173 compatible = "ti,ths8134a", "ti,ths8134";
0174 #address-cells = <1>;
0175 #size-cells = <0>;
0176
0177 ports {
0178 #address-cells = <1>;
0179 #size-cells = <0>;
0180
0181 port@0 {
0182 reg = <0>;
0183
0184 vga_bridge_in: endpoint {
0185 remote-endpoint = <&clcd_pads>;
0186 };
0187 };
0188
0189 port@1 {
0190 reg = <1>;
0191
0192 vga_bridge_out: endpoint {
0193 remote-endpoint = <&vga_con_in>;
0194 };
0195 };
0196 };
0197 };
0198
0199 vga {
0200 compatible = "vga-connector";
0201
0202 port {
0203 vga_con_in: endpoint {
0204 remote-endpoint = <&vga_bridge_out>;
0205 };
0206 };
0207 };
0208
0209 soc {
0210 #address-cells = <1>;
0211 #size-cells = <1>;
0212 compatible = "arm,realview-pb1176-soc", "simple-bus";
0213 regmap = <&syscon>;
0214 ranges;
0215
0216 syscon: syscon@10000000 {
0217 compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd";
0218 reg = <0x10000000 0x1000>;
0219 ranges = <0x0 0x10000000 0x1000>;
0220 #address-cells = <1>;
0221 #size-cells = <1>;
0222
0223 led@8,0 {
0224 compatible = "register-bit-led";
0225 reg = <0x08 0x04>;
0226 offset = <0x08>;
0227 mask = <0x01>;
0228 label = "versatile:0";
0229 linux,default-trigger = "heartbeat";
0230 default-state = "on";
0231 };
0232 led@8,1 {
0233 compatible = "register-bit-led";
0234 reg = <0x08 0x04>;
0235 offset = <0x08>;
0236 mask = <0x02>;
0237 label = "versatile:1";
0238 linux,default-trigger = "mmc0";
0239 default-state = "off";
0240 };
0241 led@8,2 {
0242 compatible = "register-bit-led";
0243 reg = <0x08 0x04>;
0244 offset = <0x08>;
0245 mask = <0x04>;
0246 label = "versatile:2";
0247 linux,default-trigger = "cpu0";
0248 default-state = "off";
0249 };
0250 led@8,3 {
0251 compatible = "register-bit-led";
0252 reg = <0x08 0x04>;
0253 offset = <0x08>;
0254 mask = <0x08>;
0255 label = "versatile:3";
0256 default-state = "off";
0257 };
0258 led@8,4 {
0259 compatible = "register-bit-led";
0260 reg = <0x08 0x04>;
0261 offset = <0x08>;
0262 mask = <0x10>;
0263 label = "versatile:4";
0264 default-state = "off";
0265 };
0266 led@8,5 {
0267 compatible = "register-bit-led";
0268 reg = <0x08 0x04>;
0269 offset = <0x08>;
0270 mask = <0x20>;
0271 label = "versatile:5";
0272 default-state = "off";
0273 };
0274 led@8,6 {
0275 compatible = "register-bit-led";
0276 reg = <0x08 0x04>;
0277 offset = <0x08>;
0278 mask = <0x40>;
0279 label = "versatile:6";
0280 default-state = "off";
0281 };
0282 led@8,7 {
0283 compatible = "register-bit-led";
0284 reg = <0x08 0x04>;
0285 offset = <0x08>;
0286 mask = <0x80>;
0287 label = "versatile:7";
0288 default-state = "off";
0289 };
0290 oscclk0: clock-controller@c {
0291 compatible = "arm,syscon-icst307";
0292 reg = <0x0c 0x04>;
0293 #clock-cells = <0>;
0294 lock-offset = <0x20>;
0295 vco-offset = <0x0C>;
0296 clocks = <&xtal24mhz>;
0297 };
0298 oscclk1: clock-controller@10 {
0299 compatible = "arm,syscon-icst307";
0300 reg = <0x10 0x04>;
0301 #clock-cells = <0>;
0302 lock-offset = <0x20>;
0303 vco-offset = <0x10>;
0304 clocks = <&xtal24mhz>;
0305 };
0306 oscclk2: clock-controller@14 {
0307 compatible = "arm,syscon-icst307";
0308 reg = <0x14 0x04>;
0309 #clock-cells = <0>;
0310 lock-offset = <0x20>;
0311 vco-offset = <0x14>;
0312 clocks = <&xtal24mhz>;
0313 };
0314 oscclk3: clock-controller@18 {
0315 compatible = "arm,syscon-icst307";
0316 reg = <0x18 0x04>;
0317 #clock-cells = <0>;
0318 lock-offset = <0x20>;
0319 vco-offset = <0x18>;
0320 clocks = <&xtal24mhz>;
0321 };
0322 oscclk4: clock-controller@1c {
0323 compatible = "arm,syscon-icst307";
0324 reg = <0x1c 0x04>;
0325 #clock-cells = <0>;
0326 lock-offset = <0x20>;
0327 vco-offset = <0x1c>;
0328 clocks = <&xtal24mhz>;
0329 };
0330 };
0331
0332 /* Primary DevChip GIC synthesized with the CPU */
0333 intc_dc1176: interrupt-controller@10120000 {
0334 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
0335 #interrupt-cells = <3>;
0336 #address-cells = <1>;
0337 interrupt-controller;
0338 reg = <0x10121000 0x1000>,
0339 <0x10120000 0x100>;
0340 };
0341
0342 L2: cache-controller {
0343 compatible = "arm,l220-cache";
0344 reg = <0x10110000 0x1000>;
0345 interrupt-parent = <&intc_dc1176>;
0346 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
0347 cache-unified;
0348 cache-level = <2>;
0349 /*
0350 * Override default cache size, sets and
0351 * associativity as these may be erroneously set
0352 * up by boot loader(s).
0353 */
0354 arm,override-auxreg;
0355 cache-size = <131072>; // 128kB
0356 cache-sets = <512>;
0357 cache-line-size = <32>;
0358 };
0359
0360 pmu {
0361 compatible = "arm,arm1176-pmu";
0362 interrupt-parent = <&intc_dc1176>;
0363 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
0364 };
0365
0366 timer01: timer@10104000 {
0367 compatible = "arm,sp804", "arm,primecell";
0368 reg = <0x10104000 0x1000>;
0369 interrupt-parent = <&intc_dc1176>;
0370 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
0371 clocks = <&timclk>, <&timclk>, <&pclk>;
0372 clock-names = "timer1", "timer2", "apb_pclk";
0373 };
0374
0375 timer23: timer@10105000 {
0376 compatible = "arm,sp804", "arm,primecell";
0377 reg = <0x10105000 0x1000>;
0378 interrupt-parent = <&intc_dc1176>;
0379 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
0380 arm,sp804-has-irq = <1>;
0381 clocks = <&timclk>, <&timclk>, <&pclk>;
0382 clock-names = "timer1", "timer2", "apb_pclk";
0383 };
0384
0385 pb1176_rtc: rtc@10108000 {
0386 compatible = "arm,pl031", "arm,primecell";
0387 reg = <0x10108000 0x1000>;
0388 interrupt-parent = <&intc_dc1176>;
0389 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
0390 clocks = <&pclk>;
0391 clock-names = "apb_pclk";
0392 };
0393
0394 pb1176_gpio0: gpio@1010a000 {
0395 compatible = "arm,pl061", "arm,primecell";
0396 reg = <0x1010a000 0x1000>;
0397 gpio-controller;
0398 interrupt-parent = <&intc_dc1176>;
0399 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
0400 #gpio-cells = <2>;
0401 interrupt-controller;
0402 #interrupt-cells = <2>;
0403 clocks = <&pclk>;
0404 clock-names = "apb_pclk";
0405 };
0406
0407 pb1176_ssp: spi@1010b000 {
0408 compatible = "arm,pl022", "arm,primecell";
0409 reg = <0x1010b000 0x1000>;
0410 interrupt-parent = <&intc_dc1176>;
0411 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
0412 clocks = <&sspclk>, <&pclk>;
0413 clock-names = "sspclk", "apb_pclk";
0414 };
0415
0416 pb1176_serial0: serial@1010c000 {
0417 compatible = "arm,pl011", "arm,primecell";
0418 reg = <0x1010c000 0x1000>;
0419 interrupt-parent = <&intc_dc1176>;
0420 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
0421 clocks = <&uartclk>, <&pclk>;
0422 clock-names = "uartclk", "apb_pclk";
0423 };
0424
0425 pb1176_serial1: serial@1010d000 {
0426 compatible = "arm,pl011", "arm,primecell";
0427 reg = <0x1010d000 0x1000>;
0428 interrupt-parent = <&intc_dc1176>;
0429 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
0430 clocks = <&uartclk>, <&pclk>;
0431 clock-names = "uartclk", "apb_pclk";
0432 };
0433
0434 pb1176_serial2: serial@1010e000 {
0435 compatible = "arm,pl011", "arm,primecell";
0436 reg = <0x1010e000 0x1000>;
0437 interrupt-parent = <&intc_dc1176>;
0438 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
0439 clocks = <&uartclk>, <&pclk>;
0440 clock-names = "uartclk", "apb_pclk";
0441 };
0442
0443 pb1176_serial3: serial@1010f000 {
0444 compatible = "arm,pl011", "arm,primecell";
0445 reg = <0x1010f000 0x1000>;
0446 interrupt-parent = <&intc_dc1176>;
0447 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
0448 clocks = <&uartclk>, <&pclk>;
0449 clock-names = "uartclk", "apb_pclk";
0450 };
0451
0452 /* Direct-mapped development chip ROM */
0453 pb1176_rom@10200000 {
0454 compatible = "direct-mapped";
0455 reg = <0x10200000 0x4000>;
0456 bank-width = <1>;
0457 };
0458
0459 clcd@10112000 {
0460 compatible = "arm,pl111", "arm,primecell";
0461 reg = <0x10112000 0x1000>;
0462 interrupt-parent = <&intc_dc1176>;
0463 interrupt-names = "combined";
0464 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
0465 clocks = <&oscclk0>, <&pclk>;
0466 clock-names = "clcdclk", "apb_pclk";
0467 /* 1024x768 16bpp @65MHz works fine */
0468 max-memory-bandwidth = <95000000>;
0469
0470 port {
0471 clcd_pads: endpoint {
0472 remote-endpoint = <&vga_bridge_in>;
0473 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
0474 };
0475 };
0476 };
0477 };
0478
0479 /* These peripherals are inside the FPGA rather than the DevChip */
0480 fpga {
0481 #address-cells = <1>;
0482 #size-cells = <1>;
0483 compatible = "simple-bus";
0484 ranges;
0485
0486 i2c0: i2c@10002000 {
0487 #address-cells = <1>;
0488 #size-cells = <0>;
0489 compatible = "arm,versatile-i2c";
0490 reg = <0x10002000 0x1000>;
0491
0492 rtc@68 {
0493 compatible = "dallas,ds1338";
0494 reg = <0x68>;
0495 };
0496 };
0497
0498 fpga_aaci: aaci@10004000 {
0499 compatible = "arm,pl041", "arm,primecell";
0500 reg = <0x10004000 0x1000>;
0501 interrupt-parent = <&intc_fpga1176>;
0502 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
0503 clocks = <&pclk>;
0504 clock-names = "apb_pclk";
0505 };
0506
0507 fpga_mci: mmcsd@10005000 {
0508 compatible = "arm,pl18x", "arm,primecell";
0509 reg = <0x10005000 0x1000>;
0510 interrupt-parent = <&intc_fpga1176>;
0511 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
0512 <0 2 IRQ_TYPE_LEVEL_HIGH>;
0513 /* Due to frequent FIFO overruns, use just 500 kHz */
0514 max-frequency = <500000>;
0515 bus-width = <4>;
0516 cap-sd-highspeed;
0517 cap-mmc-highspeed;
0518 clocks = <&mclk>, <&pclk>;
0519 clock-names = "mclk", "apb_pclk";
0520 vmmc-supply = <&vmmc>;
0521 cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
0522 wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>;
0523 };
0524
0525 fpga_kmi0: kmi@10006000 {
0526 compatible = "arm,pl050", "arm,primecell";
0527 reg = <0x10006000 0x1000>;
0528 interrupt-parent = <&intc_fpga1176>;
0529 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
0530 clocks = <&kmiclk>, <&pclk>;
0531 clock-names = "KMIREFCLK", "apb_pclk";
0532 };
0533
0534 fpga_kmi1: kmi@10007000 {
0535 compatible = "arm,pl050", "arm,primecell";
0536 reg = <0x10007000 0x1000>;
0537 interrupt-parent = <&intc_fpga1176>;
0538 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
0539 clocks = <&kmiclk>, <&pclk>;
0540 clock-names = "KMIREFCLK", "apb_pclk";
0541 };
0542
0543 fpga_charlcd: charlcd@10008000 {
0544 compatible = "arm,versatile-lcd";
0545 reg = <0x10008000 0x1000>;
0546 interrupt-parent = <&intc_fpga1176>;
0547 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
0548 clocks = <&pclk>;
0549 clock-names = "apb_pclk";
0550 };
0551
0552 fpga_serial: serial@10009000 {
0553 compatible = "arm,pl011", "arm,primecell";
0554 reg = <0x10009000 0x1000>;
0555 interrupt-parent = <&intc_fpga1176>;
0556 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
0557 clocks = <&uartclk>, <&pclk>;
0558 clock-names = "uartclk", "apb_pclk";
0559 };
0560
0561 /* This GIC on the board is cascaded off the DevChip GIC */
0562 intc_fpga1176: interrupt-controller@10040000 {
0563 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
0564 #interrupt-cells = <3>;
0565 #address-cells = <1>;
0566 interrupt-controller;
0567 reg = <0x10041000 0x1000>,
0568 <0x10040000 0x100>;
0569 interrupt-parent = <&intc_dc1176>;
0570 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
0571 };
0572
0573 fpga_gpio0: gpio@10014000 {
0574 compatible = "arm,pl061", "arm,primecell";
0575 reg = <0x10014000 0x1000>;
0576 gpio-controller;
0577 interrupt-parent = <&intc_fpga1176>;
0578 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
0579 #gpio-cells = <2>;
0580 interrupt-controller;
0581 #interrupt-cells = <2>;
0582 clocks = <&pclk>;
0583 clock-names = "apb_pclk";
0584 };
0585
0586 fpga_gpio1: gpio@10015000 {
0587 compatible = "arm,pl061", "arm,primecell";
0588 reg = <0x10015000 0x1000>;
0589 gpio-controller;
0590 interrupt-parent = <&intc_fpga1176>;
0591 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
0592 #gpio-cells = <2>;
0593 interrupt-controller;
0594 #interrupt-cells = <2>;
0595 clocks = <&pclk>;
0596 clock-names = "apb_pclk";
0597 };
0598
0599 fpga_rtc: rtc@10017000 {
0600 compatible = "arm,pl031", "arm,primecell";
0601 reg = <0x10017000 0x1000>;
0602 interrupt-parent = <&intc_fpga1176>;
0603 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
0604 clocks = <&pclk>;
0605 clock-names = "apb_pclk";
0606 };
0607 };
0608 };
