0001 /*
0002 * Copyright 2016 Linaro Ltd
0003 *
0004 * Permission is hereby granted, free of charge, to any person obtaining a copy
0005 * of this software and associated documentation files (the "Software"), to deal
0006 * in the Software without restriction, including without limitation the rights
0007 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
0008 * copies of the Software, and to permit persons to whom the Software is
0009 * furnished to do so, subject to the following conditions:
0010 *
0011 * The above copyright notice and this permission notice shall be included in
0012 * all copies or substantial portions of the Software.
0013 *
0014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
0017 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0019 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
0020 * THE SOFTWARE.
0021 */
0022
0023 #include <dt-bindings/interrupt-controller/irq.h>
0024 #include <dt-bindings/gpio/gpio.h>
0025
0026 / {
0027 #address-cells = <1>;
0028 #size-cells = <1>;
0029 compatible = "arm,realview-eb";
0030
0031 chosen { };
0032
0033 aliases {
0034 serial0 = &serial0;
0035 serial1 = &serial1;
0036 serial2 = &serial2;
0037 serial3 = &serial3;
0038 i2c0 = &i2c;
0039 };
0040
0041 memory {
0042 device_type = "memory";
0043 /* 128 MiB memory @ 0x0 */
0044 reg = <0x00000000 0x08000000>;
0045 };
0046
0047 /* The voltage to the MMC card is hardwired at 3.3V */
0048 vmmc: fixedregulator@0 {
0049 compatible = "regulator-fixed";
0050 regulator-name = "vmmc";
0051 regulator-min-microvolt = <3300000>;
0052 regulator-max-microvolt = <3300000>;
0053 regulator-boot-on;
0054 };
0055
0056 xtal24mhz: xtal24mhz@24M {
0057 #clock-cells = <0>;
0058 compatible = "fixed-clock";
0059 clock-frequency = <24000000>;
0060 };
0061
0062 timclk: timclk@1M {
0063 #clock-cells = <0>;
0064 compatible = "fixed-factor-clock";
0065 clock-div = <24>;
0066 clock-mult = <1>;
0067 clocks = <&xtal24mhz>;
0068 };
0069
0070 mclk: mclk@24M {
0071 #clock-cells = <0>;
0072 compatible = "fixed-factor-clock";
0073 clock-div = <1>;
0074 clock-mult = <1>;
0075 clocks = <&xtal24mhz>;
0076 };
0077
0078 kmiclk: kmiclk@24M {
0079 #clock-cells = <0>;
0080 compatible = "fixed-factor-clock";
0081 clock-div = <1>;
0082 clock-mult = <1>;
0083 clocks = <&xtal24mhz>;
0084 };
0085
0086 sspclk: sspclk@24M {
0087 #clock-cells = <0>;
0088 compatible = "fixed-factor-clock";
0089 clock-div = <1>;
0090 clock-mult = <1>;
0091 clocks = <&xtal24mhz>;
0092 };
0093
0094 uartclk: uartclk@24M {
0095 #clock-cells = <0>;
0096 compatible = "fixed-factor-clock";
0097 clock-div = <1>;
0098 clock-mult = <1>;
0099 clocks = <&xtal24mhz>;
0100 };
0101
0102 wdogclk: wdogclk@24M {
0103 #clock-cells = <0>;
0104 compatible = "fixed-factor-clock";
0105 clock-div = <1>;
0106 clock-mult = <1>;
0107 clocks = <&xtal24mhz>;
0108 };
0109
0110 /* FIXME: this actually hangs off the PLL clocks */
0111 pclk: pclk@0 {
0112 #clock-cells = <0>;
0113 compatible = "fixed-clock";
0114 clock-frequency = <0>;
0115 };
0116
0117 flash0@40000000 {
0118 /* 2 * 32MiB NOR Flash memory */
0119 compatible = "arm,versatile-flash", "cfi-flash";
0120 reg = <0x40000000 0x04000000>;
0121 bank-width = <4>;
0122 partitions {
0123 compatible = "arm,arm-firmware-suite";
0124 };
0125 };
0126
0127 flash1@44000000 {
0128 /* 2 * 32MiB NOR Flash memory */
0129 compatible = "arm,versatile-flash", "cfi-flash";
0130 reg = <0x44000000 0x04000000>;
0131 bank-width = <4>;
0132 partitions {
0133 compatible = "arm,arm-firmware-suite";
0134 };
0135 };
0136
0137 /* SMSC LAN91C111 ethernet with PHY and EEPROM */
0138 ethernet: ethernet@4e000000 {
0139 compatible = "smsc,lan91c111";
0140 reg = <0x4e000000 0x10000>;
0141 /*
0142 * This means the adapter can be accessed with 8, 16 or
0143 * 32 bit reads/writes.
0144 */
0145 reg-io-width = <7>;
0146 };
0147
0148 usb: usb@4f000000 {
0149 compatible = "nxp,usb-isp1761";
0150 reg = <0x4f000000 0x20000>;
0151 dr_mode = "peripheral";
0152 };
0153
0154 bridge {
0155 compatible = "ti,ths8134a", "ti,ths8134";
0156 #address-cells = <1>;
0157 #size-cells = <0>;
0158
0159 ports {
0160 #address-cells = <1>;
0161 #size-cells = <0>;
0162
0163 port@0 {
0164 reg = <0>;
0165
0166 vga_bridge_in: endpoint {
0167 remote-endpoint = <&clcd_pads>;
0168 };
0169 };
0170
0171 port@1 {
0172 reg = <1>;
0173
0174 vga_bridge_out: endpoint {
0175 remote-endpoint = <&vga_con_in>;
0176 };
0177 };
0178 };
0179 };
0180
0181 vga {
0182 compatible = "vga-connector";
0183
0184 port {
0185 vga_con_in: endpoint {
0186 remote-endpoint = <&vga_bridge_out>;
0187 };
0188 };
0189 };
0190
0191 /* These peripherals are inside the FPGA */
0192 fpga {
0193 #address-cells = <1>;
0194 #size-cells = <1>;
0195 compatible = "simple-bus";
0196 ranges;
0197
0198 syscon: syscon@10000000 {
0199 compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
0200 reg = <0x10000000 0x1000>;
0201 ranges = <0x0 0x10000000 0x1000>;
0202 #address-cells = <1>;
0203 #size-cells = <1>;
0204
0205 led@8,0 {
0206 compatible = "register-bit-led";
0207 reg = <0x08 0x04>;
0208 offset = <0x08>;
0209 mask = <0x01>;
0210 label = "versatile:0";
0211 linux,default-trigger = "heartbeat";
0212 default-state = "on";
0213 };
0214 led@8,1 {
0215 compatible = "register-bit-led";
0216 reg = <0x08 0x04>;
0217 offset = <0x08>;
0218 mask = <0x02>;
0219 label = "versatile:1";
0220 linux,default-trigger = "mmc0";
0221 default-state = "off";
0222 };
0223 led@8,2 {
0224 compatible = "register-bit-led";
0225 reg = <0x08 0x04>;
0226 offset = <0x08>;
0227 mask = <0x04>;
0228 label = "versatile:2";
0229 linux,default-trigger = "cpu0";
0230 default-state = "off";
0231 };
0232 led@8,3 {
0233 compatible = "register-bit-led";
0234 reg = <0x08 0x04>;
0235 offset = <0x08>;
0236 mask = <0x08>;
0237 label = "versatile:3";
0238 default-state = "off";
0239 };
0240 led@8,4 {
0241 compatible = "register-bit-led";
0242 reg = <0x08 0x04>;
0243 offset = <0x08>;
0244 mask = <0x10>;
0245 label = "versatile:4";
0246 default-state = "off";
0247 };
0248 led@8,5 {
0249 compatible = "register-bit-led";
0250 reg = <0x08 0x04>;
0251 offset = <0x08>;
0252 mask = <0x20>;
0253 label = "versatile:5";
0254 default-state = "off";
0255 };
0256 led@8,6 {
0257 compatible = "register-bit-led";
0258 reg = <0x08 0x04>;
0259 offset = <0x08>;
0260 mask = <0x40>;
0261 label = "versatile:6";
0262 default-state = "off";
0263 };
0264 led@8,7 {
0265 compatible = "register-bit-led";
0266 reg = <0x08 0x04>;
0267 offset = <0x08>;
0268 mask = <0x80>;
0269 label = "versatile:7";
0270 default-state = "off";
0271 };
0272 oscclk0: clock-controller@c {
0273 compatible = "arm,syscon-icst307";
0274 reg = <0x0c 0x04>;
0275 #clock-cells = <0>;
0276 lock-offset = <0x20>;
0277 vco-offset = <0x0C>;
0278 clocks = <&xtal24mhz>;
0279 };
0280 oscclk1: clock-controller@10 {
0281 compatible = "arm,syscon-icst307";
0282 reg = <0x10 0x04>;
0283 #clock-cells = <0>;
0284 lock-offset = <0x20>;
0285 vco-offset = <0x10>;
0286 clocks = <&xtal24mhz>;
0287 };
0288 oscclk2: clock-controller@14 {
0289 compatible = "arm,syscon-icst307";
0290 reg = <0x14 0x04>;
0291 #clock-cells = <0>;
0292 lock-offset = <0x20>;
0293 vco-offset = <0x14>;
0294 clocks = <&xtal24mhz>;
0295 };
0296 oscclk3: clock-controller@18 {
0297 compatible = "arm,syscon-icst307";
0298 reg = <0x18 0x04>;
0299 #clock-cells = <0>;
0300 lock-offset = <0x20>;
0301 vco-offset = <0x18>;
0302 clocks = <&xtal24mhz>;
0303 };
0304 oscclk4: clock-controller@1c {
0305 compatible = "arm,syscon-icst307";
0306 reg = <0x1c 0x04>;
0307 #clock-cells = <0>;
0308 lock-offset = <0x20>;
0309 vco-offset = <0x1c>;
0310 clocks = <&xtal24mhz>;
0311 };
0312 };
0313
0314 i2c: i2c@10002000 {
0315 #address-cells = <1>;
0316 #size-cells = <0>;
0317 compatible = "arm,versatile-i2c";
0318 reg = <0x10002000 0x1000>;
0319
0320 rtc@68 {
0321 compatible = "dallas,ds1338";
0322 reg = <0x68>;
0323 };
0324 };
0325
0326 aaci: aaci@10004000 {
0327 compatible = "arm,pl041", "arm,primecell";
0328 reg = <0x10004000 0x1000>;
0329 clocks = <&pclk>;
0330 clock-names = "apb_pclk";
0331 };
0332
0333 mmc: mmcsd@10005000 {
0334 compatible = "arm,pl18x", "arm,primecell";
0335 reg = <0x10005000 0x1000>;
0336
0337 /* Due to frequent FIFO overruns, use just 500 kHz */
0338 max-frequency = <500000>;
0339 bus-width = <4>;
0340 cap-sd-highspeed;
0341 cap-mmc-highspeed;
0342 clocks = <&mclk>, <&pclk>;
0343 clock-names = "mclk", "apb_pclk";
0344 vmmc-supply = <&vmmc>;
0345 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
0346 wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
0347 };
0348
0349 kmi0: kmi@10006000 {
0350 compatible = "arm,pl050", "arm,primecell";
0351 reg = <0x10006000 0x1000>;
0352 clocks = <&kmiclk>, <&pclk>;
0353 clock-names = "KMIREFCLK", "apb_pclk";
0354 };
0355
0356 kmi1: kmi@10007000 {
0357 compatible = "arm,pl050", "arm,primecell";
0358 reg = <0x10007000 0x1000>;
0359 clocks = <&kmiclk>, <&pclk>;
0360 clock-names = "KMIREFCLK", "apb_pclk";
0361 };
0362
0363 charlcd: fpga_charlcd: charlcd@10008000 {
0364 compatible = "arm,versatile-lcd";
0365 reg = <0x10008000 0x1000>;
0366 clocks = <&pclk>;
0367 clock-names = "apb_pclk";
0368 };
0369
0370 serial0: serial@10009000 {
0371 compatible = "arm,pl011", "arm,primecell";
0372 reg = <0x10009000 0x1000>;
0373 clocks = <&uartclk>, <&pclk>;
0374 clock-names = "uartclk", "apb_pclk";
0375 };
0376
0377 serial1: serial@1000a000 {
0378 compatible = "arm,pl011", "arm,primecell";
0379 reg = <0x1000a000 0x1000>;
0380 clocks = <&uartclk>, <&pclk>;
0381 clock-names = "uartclk", "apb_pclk";
0382 };
0383
0384 serial2: serial@1000b000 {
0385 compatible = "arm,pl011", "arm,primecell";
0386 reg = <0x1000b000 0x1000>;
0387 clocks = <&uartclk>, <&pclk>;
0388 clock-names = "uartclk", "apb_pclk";
0389 };
0390
0391 serial3: serial@1000c000 {
0392 compatible = "arm,pl011", "arm,primecell";
0393 reg = <0x1000c000 0x1000>;
0394 clocks = <&uartclk>, <&pclk>;
0395 clock-names = "uartclk", "apb_pclk";
0396 };
0397
0398 ssp: spi@1000d000 {
0399 compatible = "arm,pl022", "arm,primecell";
0400 reg = <0x1000d000 0x1000>;
0401 clocks = <&sspclk>, <&pclk>;
0402 clock-names = "sspclk", "apb_pclk";
0403 };
0404
0405 wdog: watchdog@10010000 {
0406 compatible = "arm,sp805", "arm,primecell";
0407 reg = <0x10010000 0x1000>;
0408 clocks = <&wdogclk>, <&pclk>;
0409 clock-names = "wdog_clk", "apb_pclk";
0410 status = "disabled";
0411 };
0412
0413 timer01: timer@10011000 {
0414 compatible = "arm,sp804", "arm,primecell";
0415 reg = <0x10011000 0x1000>;
0416 clocks = <&timclk>, <&timclk>, <&pclk>;
0417 clock-names = "timer1", "timer2", "apb_pclk";
0418 };
0419
0420 timer23: timer@10012000 {
0421 compatible = "arm,sp804", "arm,primecell";
0422 reg = <0x10012000 0x1000>;
0423 clocks = <&timclk>, <&timclk>, <&pclk>;
0424 clock-names = "timer1", "timer2", "apb_pclk";
0425 };
0426
0427 gpio0: gpio@10013000 {
0428 compatible = "arm,pl061", "arm,primecell";
0429 reg = <0x10013000 0x1000>;
0430 gpio-controller;
0431 #gpio-cells = <2>;
0432 interrupt-controller;
0433 #interrupt-cells = <2>;
0434 clocks = <&pclk>;
0435 clock-names = "apb_pclk";
0436 };
0437
0438 gpio1: gpio@10014000 {
0439 compatible = "arm,pl061", "arm,primecell";
0440 reg = <0x10014000 0x1000>;
0441 gpio-controller;
0442 #gpio-cells = <2>;
0443 interrupt-controller;
0444 #interrupt-cells = <2>;
0445 clocks = <&pclk>;
0446 clock-names = "apb_pclk";
0447 };
0448
0449 gpio2: gpio@10015000 {
0450 compatible = "arm,pl061", "arm,primecell";
0451 reg = <0x10015000 0x1000>;
0452 gpio-controller;
0453 #gpio-cells = <2>;
0454 interrupt-controller;
0455 #interrupt-cells = <2>;
0456 clocks = <&pclk>;
0457 clock-names = "apb_pclk";
0458 };
0459
0460 rtc: rtc@10017000 {
0461 compatible = "arm,pl031", "arm,primecell";
0462 reg = <0x10017000 0x1000>;
0463 clocks = <&pclk>;
0464 clock-names = "apb_pclk";
0465 };
0466
0467 clcd: clcd@10020000 {
0468 compatible = "arm,pl111", "arm,primecell";
0469 reg = <0x10020000 0x1000>;
0470 interrupt-names = "combined";
0471 clocks = <&oscclk0>, <&pclk>;
0472 clock-names = "clcdclk", "apb_pclk";
0473 /* 1024x768 16bpp @65MHz works fine */
0474 max-memory-bandwidth = <95000000>;
0475
0476 port {
0477 clcd_pads: endpoint {
0478 remote-endpoint = <&vga_bridge_in>;
0479 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
0480 };
0481 };
0482 };
0483 };
0484 };
