0001 /*
0002 * Copyright 2016 Linaro Ltd
0003 *
0004 * Permission is hereby granted, free of charge, to any person obtaining a copy
0005 * of this software and associated documentation files (the "Software"), to deal
0006 * in the Software without restriction, including without limitation the rights
0007 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
0008 * copies of the Software, and to permit persons to whom the Software is
0009 * furnished to do so, subject to the following conditions:
0010 *
0011 * The above copyright notice and this permission notice shall be included in
0012 * all copies or substantial portions of the Software.
0013 *
0014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
0017 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0019 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
0020 * THE SOFTWARE.
0021 */
0022
0023 /dts-v1/;
0024 #include <dt-bindings/interrupt-controller/irq.h>
0025 #include <dt-bindings/gpio/gpio.h>
0026 #include "arm-realview-eb.dtsi"
0027
0028 / {
0029 model = "ARM RealView Emulation Baseboard";
0030 compatible = "arm,realview-eb";
0031 arm,hbi = <0x140>;
0032
0033 /*
0034 * This is the core tile with the CPU and GIC etc for the
0035 * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache
0036 * or PMU.
0037 *
0038 * To run this machine with QEMU, specify the following:
0039 * qemu-system-arm -M realview-eb
0040 * Unless specified, QEMU will emulate an ARM926EJ-S core tile.
0041 * Switches -cpu arm1136 or -cpu arm1176 emulates the other
0042 * core tiles.
0043 */
0044 soc {
0045 #address-cells = <1>;
0046 #size-cells = <1>;
0047 compatible = "arm,realview-eb-soc", "simple-bus";
0048 regmap = <&syscon>;
0049 ranges;
0050
0051 intc: interrupt-controller@10040000 {
0052 compatible = "arm,pl390";
0053 #interrupt-cells = <3>;
0054 #address-cells = <1>;
0055 interrupt-controller;
0056 reg = <0x10041000 0x1000>,
0057 <0x10040000 0x100>;
0058 };
0059 };
0060 };
0061
0062 /*
0063 * This adapts all the peripherals to the interrupt routing
0064 * to the GIC on the core tile.
0065 */
0066
0067 ðernet {
0068 interrupt-parent = <&intc>;
0069 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
0070 };
0071
0072 &usb {
0073 interrupt-parent = <&intc>;
0074 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
0075 };
0076
0077 &aaci {
0078 interrupt-parent = <&intc>;
0079 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
0080 };
0081
0082 &mmc {
0083 interrupt-parent = <&intc>;
0084 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
0085 <0 18 IRQ_TYPE_LEVEL_HIGH>;
0086 };
0087
0088 &kmi0 {
0089 interrupt-parent = <&intc>;
0090 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
0091 };
0092
0093 &kmi1 {
0094 interrupt-parent = <&intc>;
0095 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
0096 };
0097
0098 &charlcd {
0099 interrupt-parent = <&intc>;
0100 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
0101 };
0102
0103 &serial0 {
0104 interrupt-parent = <&intc>;
0105 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
0106 };
0107
0108 &serial1 {
0109 interrupt-parent = <&intc>;
0110 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
0111 };
0112
0113 &serial2 {
0114 interrupt-parent = <&intc>;
0115 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
0116 };
0117
0118 &serial3 {
0119 interrupt-parent = <&intc>;
0120 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
0121 };
0122
0123 &ssp {
0124 interrupt-parent = <&intc>;
0125 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
0126 };
0127
0128 &wdog {
0129 interrupt-parent = <&intc>;
0130 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
0131 };
0132
0133 &timer01 {
0134 interrupt-parent = <&intc>;
0135 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
0136 };
0137
0138 &timer23 {
0139 interrupt-parent = <&intc>;
0140 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
0141 };
0142
0143 &gpio0 {
0144 interrupt-parent = <&intc>;
0145 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
0146 };
0147
0148 &gpio1 {
0149 interrupt-parent = <&intc>;
0150 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
0151 };
0152
0153 &gpio2 {
0154 interrupt-parent = <&intc>;
0155 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
0156 };
0157
0158 &rtc {
0159 interrupt-parent = <&intc>;
0160 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
0161 };
0162
0163 &clcd {
0164 interrupt-parent = <&intc>;
0165 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
0166 };
