0001 /*
0002 * Copyright 2016 Linaro Ltd
0003 *
0004 * Permission is hereby granted, free of charge, to any person obtaining a copy
0005 * of this software and associated documentation files (the "Software"), to deal
0006 * in the Software without restriction, including without limitation the rights
0007 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
0008 * copies of the Software, and to permit persons to whom the Software is
0009 * furnished to do so, subject to the following conditions:
0010 *
0011 * The above copyright notice and this permission notice shall be included in
0012 * all copies or substantial portions of the Software.
0013 *
0014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
0017 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0019 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
0020 * THE SOFTWARE.
0021 */
0022
0023 #include <dt-bindings/interrupt-controller/irq.h>
0024 #include <dt-bindings/gpio/gpio.h>
0025 #include "arm-realview-eb.dtsi"
0026
0027 /*
0028 * This is the common include file for all MPCore variants of the
0029 * Evaluation Baseboard, i.e. ARM11MPCore, ARM11MPCore Revision B
0030 * and Cortex-A9 MPCore.
0031 */
0032 / {
0033 soc {
0034 #address-cells = <1>;
0035 #size-cells = <1>;
0036 compatible = "arm,realview-eb-soc", "simple-bus";
0037 regmap = <&syscon>;
0038 ranges;
0039
0040 /* Primary interrupt controller in the test chip */
0041 intc: interrupt-controller@1f000100 {
0042 compatible = "arm,eb11mp-gic";
0043 #interrupt-cells = <3>;
0044 #address-cells = <1>;
0045 interrupt-controller;
0046 reg = <0x1f001000 0x1000>,
0047 <0x1f000100 0x100>;
0048 };
0049
0050 /* Secondary interrupt controller on the FPGA */
0051 intc_second: interrupt-controller@10040000 {
0052 compatible = "arm,pl390";
0053 #interrupt-cells = <3>;
0054 #address-cells = <1>;
0055 interrupt-controller;
0056 reg = <0x10041000 0x1000>,
0057 <0x10040000 0x100>;
0058 interrupt-parent = <&intc>;
0059 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
0060 };
0061
0062 L2: cache-controller {
0063 compatible = "arm,l220-cache";
0064 reg = <0x1f002000 0x1000>;
0065 interrupt-parent = <&intc>;
0066 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
0067 <0 30 IRQ_TYPE_LEVEL_HIGH>,
0068 <0 31 IRQ_TYPE_LEVEL_HIGH>;
0069 cache-unified;
0070 cache-level = <2>;
0071 /*
0072 * Override default cache size, sets and
0073 * associativity as these may be erroneously set
0074 * up by boot loader(s), probably for safety
0075 * since th outer sync operation can cause the
0076 * cache to hang unless disabled.
0077 */
0078 cache-size = <1048576>; // 1MB
0079 cache-sets = <4096>;
0080 cache-line-size = <32>;
0081 arm,shared-override;
0082 arm,parity-enable;
0083 arm,outer-sync-disable;
0084 };
0085
0086 scu: scu@1f000000 {
0087 compatible = "arm,arm11mp-scu";
0088 reg = <0x1f000000 0x100>;
0089 };
0090
0091 twd_timer: timer@1f000600 {
0092 compatible = "arm,arm11mp-twd-timer";
0093 reg = <0x1f000600 0x20>;
0094 interrupt-parent = <&intc>;
0095 interrupts = <1 13 0xf04>;
0096 };
0097
0098 twd_wdog: watchdog@1f000620 {
0099 compatible = "arm,arm11mp-twd-wdt";
0100 reg = <0x1f000620 0x20>;
0101 interrupt-parent = <&intc>;
0102 interrupts = <1 14 0xf04>;
0103 };
0104
0105 /* PMU with one IRQ line per core */
0106 pmu: pmu@0 {
0107 compatible = "arm,arm11mpcore-pmu";
0108 interrupt-parent = <&intc>;
0109 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
0110 <0 18 IRQ_TYPE_LEVEL_HIGH>,
0111 <0 19 IRQ_TYPE_LEVEL_HIGH>,
0112 <0 20 IRQ_TYPE_LEVEL_HIGH>;
0113 };
0114 };
0115 };
0116
0117 /*
0118 * This adapts all the peripherals to the interrupt routing
0119 * to the GIC on the core tile.
0120 */
0121
0122 ðernet {
0123 interrupt-parent = <&intc>;
0124 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
0125 };
0126
0127 &usb {
0128 interrupt-parent = <&intc>;
0129 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
0130 };
0131
0132 &aaci {
0133 interrupt-parent = <&intc>;
0134 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
0135 };
0136
0137 &mmc {
0138 interrupt-parent = <&intc>;
0139 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
0140 <0 15 IRQ_TYPE_LEVEL_HIGH>;
0141 };
0142
0143 &kmi0 {
0144 interrupt-parent = <&intc>;
0145 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
0146 };
0147
0148 &kmi1 {
0149 interrupt-parent = <&intc>;
0150 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
0151 };
0152
0153 &serial0 {
0154 interrupt-parent = <&intc>;
0155 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
0156 };
0157
0158 &serial1 {
0159 interrupt-parent = <&intc>;
0160 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
0161 };
0162
0163 &timer01 {
0164 interrupt-parent = <&intc>;
0165 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
0166 };
0167
0168 &timer23 {
0169 interrupt-parent = <&intc>;
0170 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
0171 };
0172
0173 &rtc {
0174 interrupt-parent = <&intc>;
0175 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
0176 };
0177
0178 /*
0179 * On revision A, these peripherals does not have their IRQ lines
0180 * routed to the core tile, but they can be reached on the secondary
0181 * GIC.
0182 */
0183 &gpio0 {
0184 interrupt-parent = <&intc_second>;
0185 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
0186 };
0187
0188 &gpio1 {
0189 interrupt-parent = <&intc_second>;
0190 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
0191 };
0192
0193 &gpio2 {
0194 interrupt-parent = <&intc_second>;
0195 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
0196 };
0197
0198 &serial2 {
0199 interrupt-parent = <&intc_second>;
0200 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
0201 status = "okay";
0202 };
0203
0204 &serial3 {
0205 interrupt-parent = <&intc_second>;
0206 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
0207 status = "okay";
0208 };
0209
0210 &ssp {
0211 interrupt-parent = <&intc_second>;
0212 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
0213 status = "okay";
0214 };
0215
0216 &wdog {
0217 interrupt-parent = <&intc_second>;
0218 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
0219 status = "okay";
0220 };
