0001 /*
0002 * Copyright 2016 Linaro Ltd
0003 *
0004 * Permission is hereby granted, free of charge, to any person obtaining a copy
0005 * of this software and associated documentation files (the "Software"), to deal
0006 * in the Software without restriction, including without limitation the rights
0007 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
0008 * copies of the Software, and to permit persons to whom the Software is
0009 * furnished to do so, subject to the following conditions:
0010 *
0011 * The above copyright notice and this permission notice shall be included in
0012 * all copies or substantial portions of the Software.
0013 *
0014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
0017 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0019 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
0020 * THE SOFTWARE.
0021 */
0022
0023 /dts-v1/;
0024 #include "arm-realview-eb-mp.dtsi"
0025
0026 / {
0027 model = "ARM RealView EB Cortex A9 MPCore";
0028
0029 /*
0030 * This is the Cortex A9 MPCore tile used with the
0031 * RealView EB.
0032 */
0033 cpus {
0034 #address-cells = <1>;
0035 #size-cells = <0>;
0036 enable-method = "arm,realview-smp";
0037
0038 A9_0: cpu@0 {
0039 device_type = "cpu";
0040 compatible = "arm,cortex-a9";
0041 reg = <0>;
0042 next-level-cache = <&L2>;
0043 };
0044
0045 A9_1: cpu@1 {
0046 device_type = "cpu";
0047 compatible = "arm,cortex-a9";
0048 reg = <1>;
0049 next-level-cache = <&L2>;
0050 };
0051
0052 A9_2: cpu@2 {
0053 device_type = "cpu";
0054 compatible = "arm,cortex-a9";
0055 reg = <2>;
0056 next-level-cache = <&L2>;
0057 };
0058
0059 A9_3: cpu@3 {
0060 device_type = "cpu";
0061 compatible = "arm,cortex-a9";
0062 reg = <3>;
0063 next-level-cache = <&L2>;
0064 };
0065 };
0066 };
0067
0068 &pmu {
0069 interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
0070 };
