0001 /*
0002 * Copyright 2016 Linaro Ltd
0003 *
0004 * Permission is hereby granted, free of charge, to any person obtaining a copy
0005 * of this software and associated documentation files (the "Software"), to deal
0006 * in the Software without restriction, including without limitation the rights
0007 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
0008 * copies of the Software, and to permit persons to whom the Software is
0009 * furnished to do so, subject to the following conditions:
0010 *
0011 * The above copyright notice and this permission notice shall be included in
0012 * all copies or substantial portions of the Software.
0013 *
0014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
0017 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0019 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
0020 * THE SOFTWARE.
0021 */
0022
0023 /dts-v1/;
0024 #include "arm-realview-eb-mp.dtsi"
0025
0026 / {
0027 model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C Core Tile";
0028 arm,hbi = <0x146>;
0029
0030 /*
0031 * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.
0032 * Reference: ARM DUI 0318F
0033 *
0034 * To run this machine with QEMU, specify the following:
0035 * qemu-system-arm -M realview-eb-mpcore -smp cpus=4
0036 */
0037 cpus {
0038 #address-cells = <1>;
0039 #size-cells = <0>;
0040 enable-method = "arm,realview-smp";
0041
0042 MP11_0: cpu@0 {
0043 device_type = "cpu";
0044 compatible = "arm,arm11mpcore";
0045 reg = <0>;
0046 next-level-cache = <&L2>;
0047 };
0048
0049 MP11_1: cpu@1 {
0050 device_type = "cpu";
0051 compatible = "arm,arm11mpcore";
0052 reg = <1>;
0053 next-level-cache = <&L2>;
0054 };
0055
0056 MP11_2: cpu@2 {
0057 device_type = "cpu";
0058 compatible = "arm,arm11mpcore";
0059 reg = <2>;
0060 next-level-cache = <&L2>;
0061 };
0062
0063 MP11_3: cpu@3 {
0064 device_type = "cpu";
0065 compatible = "arm,arm11mpcore";
0066 reg = <3>;
0067 next-level-cache = <&L2>;
0068 };
0069 };
0070 };
0071
0072 &pmu {
0073 interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
0074 };
