0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for AM43xx clock data
0004 *
0005 * Copyright (C) 2013 Texas Instruments, Inc.
0006 */
0007 &scm_clocks {
0008 sys_clkin_ck: clock-sys-clkin-31@40 {
0009 #clock-cells = <0>;
0010 compatible = "ti,mux-clock";
0011 clock-output-names = "sys_clkin_ck";
0012 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
0013 ti,bit-shift = <31>;
0014 reg = <0x0040>;
0015 };
0016
0017 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
0018 #clock-cells = <0>;
0019 compatible = "ti,mux-clock";
0020 clock-output-names = "crystal_freq_sel_ck";
0021 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
0022 ti,bit-shift = <29>;
0023 reg = <0x0040>;
0024 };
0025
0026 sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 {
0027 #clock-cells = <0>;
0028 compatible = "ti,mux-clock";
0029 clock-output-names = "sysboot_freq_sel_ck";
0030 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
0031 ti,bit-shift = <22>;
0032 reg = <0x0040>;
0033 };
0034
0035 adc_tsc_fck: clock-adc-tsc-fck {
0036 #clock-cells = <0>;
0037 compatible = "fixed-factor-clock";
0038 clock-output-names = "adc_tsc_fck";
0039 clocks = <&sys_clkin_ck>;
0040 clock-mult = <1>;
0041 clock-div = <1>;
0042 };
0043
0044 dcan0_fck: clock-dcan0-fck {
0045 #clock-cells = <0>;
0046 compatible = "fixed-factor-clock";
0047 clock-output-names = "dcan0_fck";
0048 clocks = <&sys_clkin_ck>;
0049 clock-mult = <1>;
0050 clock-div = <1>;
0051 };
0052
0053 dcan1_fck: clock-dcan1-fck {
0054 #clock-cells = <0>;
0055 compatible = "fixed-factor-clock";
0056 clock-output-names = "dcan1_fck";
0057 clocks = <&sys_clkin_ck>;
0058 clock-mult = <1>;
0059 clock-div = <1>;
0060 };
0061
0062 mcasp0_fck: clock-mcasp0-fck {
0063 #clock-cells = <0>;
0064 compatible = "fixed-factor-clock";
0065 clock-output-names = "mcasp0_fck";
0066 clocks = <&sys_clkin_ck>;
0067 clock-mult = <1>;
0068 clock-div = <1>;
0069 };
0070
0071 mcasp1_fck: clock-mcasp1-fck {
0072 #clock-cells = <0>;
0073 compatible = "fixed-factor-clock";
0074 clock-output-names = "mcasp1_fck";
0075 clocks = <&sys_clkin_ck>;
0076 clock-mult = <1>;
0077 clock-div = <1>;
0078 };
0079
0080 smartreflex0_fck: clock-smartreflex0-fck {
0081 #clock-cells = <0>;
0082 compatible = "fixed-factor-clock";
0083 clock-output-names = "smartreflex0_fck";
0084 clocks = <&sys_clkin_ck>;
0085 clock-mult = <1>;
0086 clock-div = <1>;
0087 };
0088
0089 smartreflex1_fck: clock-smartreflex1-fck {
0090 #clock-cells = <0>;
0091 compatible = "fixed-factor-clock";
0092 clock-output-names = "smartreflex1_fck";
0093 clocks = <&sys_clkin_ck>;
0094 clock-mult = <1>;
0095 clock-div = <1>;
0096 };
0097
0098 sha0_fck: clock-sha0-fck {
0099 #clock-cells = <0>;
0100 compatible = "fixed-factor-clock";
0101 clock-output-names = "sha0_fck";
0102 clocks = <&sys_clkin_ck>;
0103 clock-mult = <1>;
0104 clock-div = <1>;
0105 };
0106
0107 aes0_fck: clock-aes0-fck {
0108 #clock-cells = <0>;
0109 compatible = "fixed-factor-clock";
0110 clock-output-names = "aes0_fck";
0111 clocks = <&sys_clkin_ck>;
0112 clock-mult = <1>;
0113 clock-div = <1>;
0114 };
0115
0116 rng_fck: clock-rng-fck {
0117 #clock-cells = <0>;
0118 compatible = "fixed-factor-clock";
0119 clock-output-names = "rng_fck";
0120 clocks = <&sys_clkin_ck>;
0121 clock-mult = <1>;
0122 clock-div = <1>;
0123 };
0124
0125 ehrpwm0_tbclk: clock-ehrpwm0-tbclk-0@664 {
0126 #clock-cells = <0>;
0127 compatible = "ti,gate-clock";
0128 clock-output-names = "ehrpwm0_tbclk";
0129 clocks = <&l4ls_gclk>;
0130 ti,bit-shift = <0>;
0131 reg = <0x0664>;
0132 };
0133
0134 ehrpwm1_tbclk: clock-ehrpwm1-tbclk-1@664 {
0135 #clock-cells = <0>;
0136 compatible = "ti,gate-clock";
0137 clock-output-names = "ehrpwm1_tbclk";
0138 clocks = <&l4ls_gclk>;
0139 ti,bit-shift = <1>;
0140 reg = <0x0664>;
0141 };
0142
0143 ehrpwm2_tbclk: clock-ehrpwm2-tbclk-2@664 {
0144 #clock-cells = <0>;
0145 compatible = "ti,gate-clock";
0146 clock-output-names = "ehrpwm2_tbclk";
0147 clocks = <&l4ls_gclk>;
0148 ti,bit-shift = <2>;
0149 reg = <0x0664>;
0150 };
0151
0152 ehrpwm3_tbclk: clock-ehrpwm3-tbclk-4@664 {
0153 #clock-cells = <0>;
0154 compatible = "ti,gate-clock";
0155 clock-output-names = "ehrpwm3_tbclk";
0156 clocks = <&l4ls_gclk>;
0157 ti,bit-shift = <4>;
0158 reg = <0x0664>;
0159 };
0160
0161 ehrpwm4_tbclk: clock-ehrpwm4-tbclk-5@664 {
0162 #clock-cells = <0>;
0163 compatible = "ti,gate-clock";
0164 clock-output-names = "ehrpwm4_tbclk";
0165 clocks = <&l4ls_gclk>;
0166 ti,bit-shift = <5>;
0167 reg = <0x0664>;
0168 };
0169
0170 ehrpwm5_tbclk: clock-ehrpwm5-tbclk-6@664 {
0171 #clock-cells = <0>;
0172 compatible = "ti,gate-clock";
0173 clock-output-names = "ehrpwm5_tbclk";
0174 clocks = <&l4ls_gclk>;
0175 ti,bit-shift = <6>;
0176 reg = <0x0664>;
0177 };
0178 };
0179 &prcm_clocks {
0180 clk_32768_ck: clock-clk-32768 {
0181 #clock-cells = <0>;
0182 compatible = "fixed-clock";
0183 clock-output-names = "clk_32768_ck";
0184 clock-frequency = <32768>;
0185 };
0186
0187 clk_rc32k_ck: clock-clk-rc32k {
0188 #clock-cells = <0>;
0189 compatible = "fixed-clock";
0190 clock-output-names = "clk_rc32k_ck";
0191 clock-frequency = <32768>;
0192 };
0193
0194 virt_19200000_ck: clock-virt-19200000 {
0195 #clock-cells = <0>;
0196 compatible = "fixed-clock";
0197 clock-output-names = "virt_19200000_ck";
0198 clock-frequency = <19200000>;
0199 };
0200
0201 virt_24000000_ck: clock-virt-24000000 {
0202 #clock-cells = <0>;
0203 compatible = "fixed-clock";
0204 clock-output-names = "virt_24000000_ck";
0205 clock-frequency = <24000000>;
0206 };
0207
0208 virt_25000000_ck: clock-virt-25000000 {
0209 #clock-cells = <0>;
0210 compatible = "fixed-clock";
0211 clock-output-names = "virt_25000000_ck";
0212 clock-frequency = <25000000>;
0213 };
0214
0215 virt_26000000_ck: clock-virt-26000000 {
0216 #clock-cells = <0>;
0217 compatible = "fixed-clock";
0218 clock-output-names = "virt_26000000_ck";
0219 clock-frequency = <26000000>;
0220 };
0221
0222 tclkin_ck: clock-tclkin {
0223 #clock-cells = <0>;
0224 compatible = "fixed-clock";
0225 clock-output-names = "tclkin_ck";
0226 clock-frequency = <26000000>;
0227 };
0228
0229 dpll_core_ck: clock@2d20 {
0230 #clock-cells = <0>;
0231 compatible = "ti,am3-dpll-core-clock";
0232 clock-output-names = "dpll_core_ck";
0233 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
0234 reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
0235 };
0236
0237 dpll_core_x2_ck: clock-dpll-core-x2 {
0238 #clock-cells = <0>;
0239 compatible = "ti,am3-dpll-x2-clock";
0240 clock-output-names = "dpll_core_x2_ck";
0241 clocks = <&dpll_core_ck>;
0242 };
0243
0244 dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
0245 #clock-cells = <0>;
0246 compatible = "ti,divider-clock";
0247 clock-output-names = "dpll_core_m4_ck";
0248 clocks = <&dpll_core_x2_ck>;
0249 ti,max-div = <31>;
0250 ti,autoidle-shift = <8>;
0251 reg = <0x2d38>;
0252 ti,index-starts-at-one;
0253 ti,invert-autoidle-bit;
0254 };
0255
0256 dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
0257 #clock-cells = <0>;
0258 compatible = "ti,divider-clock";
0259 clock-output-names = "dpll_core_m5_ck";
0260 clocks = <&dpll_core_x2_ck>;
0261 ti,max-div = <31>;
0262 ti,autoidle-shift = <8>;
0263 reg = <0x2d3c>;
0264 ti,index-starts-at-one;
0265 ti,invert-autoidle-bit;
0266 };
0267
0268 dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
0269 #clock-cells = <0>;
0270 compatible = "ti,divider-clock";
0271 clock-output-names = "dpll_core_m6_ck";
0272 clocks = <&dpll_core_x2_ck>;
0273 ti,max-div = <31>;
0274 ti,autoidle-shift = <8>;
0275 reg = <0x2d40>;
0276 ti,index-starts-at-one;
0277 ti,invert-autoidle-bit;
0278 };
0279
0280 dpll_mpu_ck: clock@2d60 {
0281 #clock-cells = <0>;
0282 compatible = "ti,am3-dpll-clock";
0283 clock-output-names = "dpll_mpu_ck";
0284 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
0285 reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
0286 };
0287
0288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
0289 #clock-cells = <0>;
0290 compatible = "ti,divider-clock";
0291 clock-output-names = "dpll_mpu_m2_ck";
0292 clocks = <&dpll_mpu_ck>;
0293 ti,max-div = <31>;
0294 ti,autoidle-shift = <8>;
0295 reg = <0x2d70>;
0296 ti,index-starts-at-one;
0297 ti,invert-autoidle-bit;
0298 };
0299
0300 mpu_periphclk: clock-mpu-periphclk {
0301 #clock-cells = <0>;
0302 compatible = "fixed-factor-clock";
0303 clock-output-names = "mpu_periphclk";
0304 clocks = <&dpll_mpu_m2_ck>;
0305 clock-mult = <1>;
0306 clock-div = <2>;
0307 };
0308
0309 dpll_ddr_ck: clock@2da0 {
0310 #clock-cells = <0>;
0311 compatible = "ti,am3-dpll-clock";
0312 clock-output-names = "dpll_ddr_ck";
0313 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
0314 reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
0315 };
0316
0317 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
0318 #clock-cells = <0>;
0319 compatible = "ti,divider-clock";
0320 clock-output-names = "dpll_ddr_m2_ck";
0321 clocks = <&dpll_ddr_ck>;
0322 ti,max-div = <31>;
0323 ti,autoidle-shift = <8>;
0324 reg = <0x2db0>;
0325 ti,index-starts-at-one;
0326 ti,invert-autoidle-bit;
0327 };
0328
0329 dpll_disp_ck: clock@2e20 {
0330 #clock-cells = <0>;
0331 compatible = "ti,am3-dpll-clock";
0332 clock-output-names = "dpll_disp_ck";
0333 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
0334 reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
0335 };
0336
0337 dpll_disp_m2_ck: clock-dpll-disp-m2-8@2e30 {
0338 #clock-cells = <0>;
0339 compatible = "ti,divider-clock";
0340 clock-output-names = "dpll_disp_m2_ck";
0341 clocks = <&dpll_disp_ck>;
0342 ti,max-div = <31>;
0343 ti,autoidle-shift = <8>;
0344 reg = <0x2e30>;
0345 ti,index-starts-at-one;
0346 ti,invert-autoidle-bit;
0347 ti,set-rate-parent;
0348 };
0349
0350 dpll_per_ck: clock@2de0 {
0351 #clock-cells = <0>;
0352 compatible = "ti,am3-dpll-j-type-clock";
0353 clock-output-names = "dpll_per_ck";
0354 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
0355 reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
0356 };
0357
0358 dpll_per_m2_ck: clock-dpll-per-m2-8@2df0 {
0359 #clock-cells = <0>;
0360 compatible = "ti,divider-clock";
0361 clock-output-names = "dpll_per_m2_ck";
0362 clocks = <&dpll_per_ck>;
0363 ti,max-div = <127>;
0364 ti,autoidle-shift = <8>;
0365 reg = <0x2df0>;
0366 ti,index-starts-at-one;
0367 ti,invert-autoidle-bit;
0368 };
0369
0370 dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
0371 #clock-cells = <0>;
0372 compatible = "fixed-factor-clock";
0373 clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
0374 clocks = <&dpll_per_m2_ck>;
0375 clock-mult = <1>;
0376 clock-div = <4>;
0377 };
0378
0379 dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
0380 #clock-cells = <0>;
0381 compatible = "fixed-factor-clock";
0382 clock-output-names = "dpll_per_m2_div4_ck";
0383 clocks = <&dpll_per_m2_ck>;
0384 clock-mult = <1>;
0385 clock-div = <4>;
0386 };
0387
0388 clk_24mhz: clock-clk-24mhz {
0389 #clock-cells = <0>;
0390 compatible = "fixed-factor-clock";
0391 clock-output-names = "clk_24mhz";
0392 clocks = <&dpll_per_m2_ck>;
0393 clock-mult = <1>;
0394 clock-div = <8>;
0395 };
0396
0397 clkdiv32k_ck: clock-clkdiv32k {
0398 #clock-cells = <0>;
0399 compatible = "fixed-factor-clock";
0400 clock-output-names = "clkdiv32k_ck";
0401 clocks = <&clk_24mhz>;
0402 clock-mult = <1>;
0403 clock-div = <732>;
0404 };
0405
0406 clkdiv32k_ick: clock-clkdiv32k-ick-8@2a38 {
0407 #clock-cells = <0>;
0408 compatible = "ti,gate-clock";
0409 clock-output-names = "clkdiv32k_ick";
0410 clocks = <&clkdiv32k_ck>;
0411 ti,bit-shift = <8>;
0412 reg = <0x2a38>;
0413 };
0414
0415 sysclk_div: clock-sysclk-div {
0416 #clock-cells = <0>;
0417 compatible = "fixed-factor-clock";
0418 clock-output-names = "sysclk_div";
0419 clocks = <&dpll_core_m4_ck>;
0420 clock-mult = <1>;
0421 clock-div = <1>;
0422 };
0423
0424 pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 {
0425 #clock-cells = <0>;
0426 compatible = "ti,mux-clock";
0427 clock-output-names = "pruss_ocp_gclk";
0428 clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
0429 reg = <0x4248>;
0430 };
0431
0432 clk_32k_tpm_ck: clock-clk-32k-tpm {
0433 #clock-cells = <0>;
0434 compatible = "fixed-clock";
0435 clock-output-names = "clk_32k_tpm_ck";
0436 clock-frequency = <32768>;
0437 };
0438
0439 timer1_fck: clock-timer1-fck@4200 {
0440 #clock-cells = <0>;
0441 compatible = "ti,mux-clock";
0442 clock-output-names = "timer1_fck";
0443 clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
0444 reg = <0x4200>;
0445 };
0446
0447 timer2_fck: clock-timer2-fck@4204 {
0448 #clock-cells = <0>;
0449 compatible = "ti,mux-clock";
0450 clock-output-names = "timer2_fck";
0451 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
0452 reg = <0x4204>;
0453 };
0454
0455 timer3_fck: clock-timer3-fck@4208 {
0456 #clock-cells = <0>;
0457 compatible = "ti,mux-clock";
0458 clock-output-names = "timer3_fck";
0459 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
0460 reg = <0x4208>;
0461 };
0462
0463 timer4_fck: clock-timer4-fck@420c {
0464 #clock-cells = <0>;
0465 compatible = "ti,mux-clock";
0466 clock-output-names = "timer4_fck";
0467 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
0468 reg = <0x420c>;
0469 };
0470
0471 timer5_fck: clock-timer5-fck@4210 {
0472 #clock-cells = <0>;
0473 compatible = "ti,mux-clock";
0474 clock-output-names = "timer5_fck";
0475 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
0476 reg = <0x4210>;
0477 };
0478
0479 timer6_fck: clock-timer6-fck@4214 {
0480 #clock-cells = <0>;
0481 compatible = "ti,mux-clock";
0482 clock-output-names = "timer6_fck";
0483 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
0484 reg = <0x4214>;
0485 };
0486
0487 timer7_fck: clock-timer7-fck@4218 {
0488 #clock-cells = <0>;
0489 compatible = "ti,mux-clock";
0490 clock-output-names = "timer7_fck";
0491 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
0492 reg = <0x4218>;
0493 };
0494
0495 wdt1_fck: clock-wdt1-fck@422c {
0496 #clock-cells = <0>;
0497 compatible = "ti,mux-clock";
0498 clock-output-names = "wdt1_fck";
0499 clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
0500 reg = <0x422c>;
0501 };
0502
0503 adc_mag_fck: adc_mag_fck@424c {
0504 #clock-cells = <0>;
0505 compatible = "ti,mux-clock";
0506 clocks = <&sys_clkin_ck>, <&dpll_per_m2_ck>;
0507 reg = <0x424c>;
0508 };
0509
0510 l3_gclk: clock-l3-gclk {
0511 #clock-cells = <0>;
0512 compatible = "fixed-factor-clock";
0513 clock-output-names = "l3_gclk";
0514 clocks = <&dpll_core_m4_ck>;
0515 clock-mult = <1>;
0516 clock-div = <1>;
0517 };
0518
0519 dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
0520 #clock-cells = <0>;
0521 compatible = "fixed-factor-clock";
0522 clock-output-names = "dpll_core_m4_div2_ck";
0523 clocks = <&sysclk_div>;
0524 clock-mult = <1>;
0525 clock-div = <2>;
0526 };
0527
0528 l4hs_gclk: clock-l4hs-gclk {
0529 #clock-cells = <0>;
0530 compatible = "fixed-factor-clock";
0531 clock-output-names = "l4hs_gclk";
0532 clocks = <&dpll_core_m4_ck>;
0533 clock-mult = <1>;
0534 clock-div = <1>;
0535 };
0536
0537 l3s_gclk: clock-l3s-gclk {
0538 #clock-cells = <0>;
0539 compatible = "fixed-factor-clock";
0540 clock-output-names = "l3s_gclk";
0541 clocks = <&dpll_core_m4_div2_ck>;
0542 clock-mult = <1>;
0543 clock-div = <1>;
0544 };
0545
0546 l4ls_gclk: clock-l4ls-gclk {
0547 #clock-cells = <0>;
0548 compatible = "fixed-factor-clock";
0549 clock-output-names = "l4ls_gclk";
0550 clocks = <&dpll_core_m4_div2_ck>;
0551 clock-mult = <1>;
0552 clock-div = <1>;
0553 };
0554
0555 cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
0556 #clock-cells = <0>;
0557 compatible = "fixed-factor-clock";
0558 clock-output-names = "cpsw_125mhz_gclk";
0559 clocks = <&dpll_core_m5_ck>;
0560 clock-mult = <1>;
0561 clock-div = <2>;
0562 };
0563
0564 cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@4238 {
0565 #clock-cells = <0>;
0566 compatible = "ti,mux-clock";
0567 clock-output-names = "cpsw_cpts_rft_clk";
0568 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
0569 reg = <0x4238>;
0570 };
0571
0572 dpll_clksel_mac_clk: clock-dpll-clksel-mac-2@4234 {
0573 #clock-cells = <0>;
0574 compatible = "ti,divider-clock";
0575 clock-output-names = "dpll_clksel_mac_clk";
0576 clocks = <&dpll_core_m5_ck>;
0577 reg = <0x4234>;
0578 ti,bit-shift = <2>;
0579 ti,dividers = <2>, <5>;
0580 };
0581
0582 clk_32k_mosc_ck: clock-clk-32k-mosc {
0583 #clock-cells = <0>;
0584 compatible = "fixed-clock";
0585 clock-output-names = "clk_32k_mosc_ck";
0586 clock-frequency = <32768>;
0587 };
0588
0589 gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@4240 {
0590 #clock-cells = <0>;
0591 compatible = "ti,mux-clock";
0592 clock-output-names = "gpio0_dbclk_mux_ck";
0593 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
0594 reg = <0x4240>;
0595 };
0596
0597 mmc_clk: clock-mmc {
0598 #clock-cells = <0>;
0599 compatible = "fixed-factor-clock";
0600 clock-output-names = "mmc_clk";
0601 clocks = <&dpll_per_m2_ck>;
0602 clock-mult = <1>;
0603 clock-div = <2>;
0604 };
0605
0606 gfx_fclk_clksel_ck: clock-gfx-fclk-clksel-1@423c {
0607 #clock-cells = <0>;
0608 compatible = "ti,mux-clock";
0609 clock-output-names = "gfx_fclk_clksel_ck";
0610 clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
0611 ti,bit-shift = <1>;
0612 reg = <0x423c>;
0613 };
0614
0615 gfx_fck_div_ck: clock-gfx-fck-div@423c {
0616 #clock-cells = <0>;
0617 compatible = "ti,divider-clock";
0618 clock-output-names = "gfx_fck_div_ck";
0619 clocks = <&gfx_fclk_clksel_ck>;
0620 reg = <0x423c>;
0621 ti,max-div = <2>;
0622 };
0623
0624 disp_clk: clock-disp@4244 {
0625 #clock-cells = <0>;
0626 compatible = "ti,mux-clock";
0627 clock-output-names = "disp_clk";
0628 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
0629 reg = <0x4244>;
0630 ti,set-rate-parent;
0631 };
0632
0633 dpll_extdev_ck: clock@2e60 {
0634 #clock-cells = <0>;
0635 compatible = "ti,am3-dpll-clock";
0636 clock-output-names = "dpll_extdev_ck";
0637 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
0638 reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
0639 };
0640
0641 dpll_extdev_m2_ck: clock-dpll-extdev-m2-8@2e70 {
0642 #clock-cells = <0>;
0643 compatible = "ti,divider-clock";
0644 clock-output-names = "dpll_extdev_m2_ck";
0645 clocks = <&dpll_extdev_ck>;
0646 ti,max-div = <127>;
0647 ti,autoidle-shift = <8>;
0648 reg = <0x2e70>;
0649 ti,index-starts-at-one;
0650 ti,invert-autoidle-bit;
0651 };
0652
0653 mux_synctimer32k_ck: clock-mux-synctimer32k@4230 {
0654 #clock-cells = <0>;
0655 compatible = "ti,mux-clock";
0656 clock-output-names = "mux_synctimer32k_ck";
0657 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
0658 reg = <0x4230>;
0659 };
0660
0661 timer8_fck: clock-timer8-fck@421c {
0662 #clock-cells = <0>;
0663 compatible = "ti,mux-clock";
0664 clock-output-names = "timer8_fck";
0665 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
0666 reg = <0x421c>;
0667 };
0668
0669 timer9_fck: clock-timer9-fck@4220 {
0670 #clock-cells = <0>;
0671 compatible = "ti,mux-clock";
0672 clock-output-names = "timer9_fck";
0673 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
0674 reg = <0x4220>;
0675 };
0676
0677 timer10_fck: clock-timer10-fck@4224 {
0678 #clock-cells = <0>;
0679 compatible = "ti,mux-clock";
0680 clock-output-names = "timer10_fck";
0681 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
0682 reg = <0x4224>;
0683 };
0684
0685 timer11_fck: clock-timer11-fck@4228 {
0686 #clock-cells = <0>;
0687 compatible = "ti,mux-clock";
0688 clock-output-names = "timer11_fck";
0689 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
0690 reg = <0x4228>;
0691 };
0692
0693 cpsw_50m_clkdiv: clock-cpsw-50m-clkdiv {
0694 #clock-cells = <0>;
0695 compatible = "fixed-factor-clock";
0696 clock-output-names = "cpsw_50m_clkdiv";
0697 clocks = <&dpll_core_m5_ck>;
0698 clock-mult = <1>;
0699 clock-div = <1>;
0700 };
0701
0702 cpsw_5m_clkdiv: clock-cpsw-5m-clkdiv {
0703 #clock-cells = <0>;
0704 compatible = "fixed-factor-clock";
0705 clock-output-names = "cpsw_5m_clkdiv";
0706 clocks = <&cpsw_50m_clkdiv>;
0707 clock-mult = <1>;
0708 clock-div = <10>;
0709 };
0710
0711 dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
0712 #clock-cells = <0>;
0713 compatible = "ti,am3-dpll-x2-clock";
0714 clock-output-names = "dpll_ddr_x2_ck";
0715 clocks = <&dpll_ddr_ck>;
0716 };
0717
0718 dpll_ddr_m4_ck: clock-dpll-ddr-m4-8@2db8 {
0719 #clock-cells = <0>;
0720 compatible = "ti,divider-clock";
0721 clock-output-names = "dpll_ddr_m4_ck";
0722 clocks = <&dpll_ddr_x2_ck>;
0723 ti,max-div = <31>;
0724 ti,autoidle-shift = <8>;
0725 reg = <0x2db8>;
0726 ti,index-starts-at-one;
0727 ti,invert-autoidle-bit;
0728 };
0729
0730 dpll_per_clkdcoldo: clock-dpll-per-clkdcoldo-8@2e14 {
0731 #clock-cells = <0>;
0732 compatible = "ti,fixed-factor-clock";
0733 clock-output-names = "dpll_per_clkdcoldo";
0734 clocks = <&dpll_per_ck>;
0735 ti,clock-mult = <1>;
0736 ti,clock-div = <1>;
0737 ti,autoidle-shift = <8>;
0738 reg = <0x2e14>;
0739 ti,invert-autoidle-bit;
0740 };
0741
0742 dll_aging_clk_div: clock-dll-aging-clk-div@4250 {
0743 #clock-cells = <0>;
0744 compatible = "ti,divider-clock";
0745 clock-output-names = "dll_aging_clk_div";
0746 clocks = <&sys_clkin_ck>;
0747 reg = <0x4250>;
0748 ti,dividers = <8>, <16>, <32>;
0749 };
0750
0751 div_core_25m_ck: clock-div-core-25m {
0752 #clock-cells = <0>;
0753 compatible = "fixed-factor-clock";
0754 clock-output-names = "div_core_25m_ck";
0755 clocks = <&sysclk_div>;
0756 clock-mult = <1>;
0757 clock-div = <8>;
0758 };
0759
0760 func_12m_clk: clock-func-12m {
0761 #clock-cells = <0>;
0762 compatible = "fixed-factor-clock";
0763 clock-output-names = "func_12m_clk";
0764 clocks = <&dpll_per_m2_ck>;
0765 clock-mult = <1>;
0766 clock-div = <16>;
0767 };
0768
0769 vtp_clk_div: clock-vtp-clk-div {
0770 #clock-cells = <0>;
0771 compatible = "fixed-factor-clock";
0772 clock-output-names = "vtp_clk_div";
0773 clocks = <&sys_clkin_ck>;
0774 clock-mult = <1>;
0775 clock-div = <2>;
0776 };
0777
0778 usbphy_32khz_clkmux: clock-usbphy-32khz-clkmux@4260 {
0779 #clock-cells = <0>;
0780 compatible = "ti,mux-clock";
0781 clock-output-names = "usbphy_32khz_clkmux";
0782 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
0783 reg = <0x4260>;
0784 };
0785
0786 usb_phy0_always_on_clk32k: clock-usb-phy0-always-on-clk32k-8@2a40 {
0787 #clock-cells = <0>;
0788 compatible = "ti,gate-clock";
0789 clock-output-names = "usb_phy0_always_on_clk32k";
0790 clocks = <&usbphy_32khz_clkmux>;
0791 ti,bit-shift = <8>;
0792 reg = <0x2a40>;
0793 };
0794
0795 usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@2a48 {
0796 #clock-cells = <0>;
0797 compatible = "ti,gate-clock";
0798 clock-output-names = "usb_phy1_always_on_clk32k";
0799 clocks = <&usbphy_32khz_clkmux>;
0800 ti,bit-shift = <8>;
0801 reg = <0x2a48>;
0802 };
0803
0804 clkout1_osc_div_ck: clock-clkout1-osc-div-ck {
0805 #clock-cells = <0>;
0806 compatible = "ti,divider-clock";
0807 clock-output-names = "clkout1_osc_div_ck";
0808 clocks = <&sys_clkin_ck>;
0809 ti,bit-shift = <20>;
0810 ti,max-div = <4>;
0811 reg = <0x4100>;
0812 };
0813
0814 clkout1_src2_mux_ck: clock-clkout1-src2-mux-ck {
0815 #clock-cells = <0>;
0816 compatible = "ti,mux-clock";
0817 clock-output-names = "clkout1_src2_mux_ck";
0818 clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
0819 <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
0820 <&dpll_mpu_m2_ck>;
0821 reg = <0x4100>;
0822 };
0823
0824 clkout1_src2_pre_div_ck: clock-clkout1-src2-pre-div-ck {
0825 #clock-cells = <0>;
0826 compatible = "ti,divider-clock";
0827 clock-output-names = "clkout1_src2_pre_div_ck";
0828 clocks = <&clkout1_src2_mux_ck>;
0829 ti,bit-shift = <4>;
0830 ti,max-div = <8>;
0831 reg = <0x4100>;
0832 };
0833
0834 clkout1_src2_post_div_ck: clock-clkout1-src2-post-div-ck {
0835 #clock-cells = <0>;
0836 compatible = "ti,divider-clock";
0837 clock-output-names = "clkout1_src2_post_div_ck";
0838 clocks = <&clkout1_src2_pre_div_ck>;
0839 ti,bit-shift = <8>;
0840 ti,max-div = <32>;
0841 ti,index-power-of-two;
0842 reg = <0x4100>;
0843 };
0844
0845 clkout1_mux_ck: clock-clkout1-mux-ck {
0846 #clock-cells = <0>;
0847 compatible = "ti,mux-clock";
0848 clock-output-names = "clkout1_mux_ck";
0849 clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
0850 <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
0851 ti,bit-shift = <16>;
0852 reg = <0x4100>;
0853 };
0854
0855 clkout1_ck: clock-clkout1-ck {
0856 #clock-cells = <0>;
0857 compatible = "ti,gate-clock";
0858 clock-output-names = "clkout1_ck";
0859 clocks = <&clkout1_mux_ck>;
0860 ti,bit-shift = <23>;
0861 reg = <0x4100>;
0862 };
0863 };
0864
0865 &prcm {
0866 wkup_cm: clock@2800 {
0867 compatible = "ti,omap4-cm";
0868 clock-output-names = "wkup_cm";
0869 reg = <0x2800 0x400>;
0870 #address-cells = <1>;
0871 #size-cells = <1>;
0872 ranges = <0 0x2800 0x400>;
0873
0874 l3s_tsc_clkctrl: clock@120 {
0875 compatible = "ti,clkctrl";
0876 clock-output-names = "l3s_tsc_clkctrl";
0877 reg = <0x120 0x4>;
0878 #clock-cells = <2>;
0879 };
0880
0881 l4_wkup_aon_clkctrl: clock@228 {
0882 compatible = "ti,clkctrl";
0883 clock-output-names = "l4_wkup_aon_clkctrl";
0884 reg = <0x228 0xc>;
0885 #clock-cells = <2>;
0886 };
0887
0888 l4_wkup_clkctrl: clock@220 {
0889 compatible = "ti,clkctrl";
0890 clock-output-names = "l4_wkup_clkctrl";
0891 reg = <0x220 0x4>, <0x328 0x44>;
0892 #clock-cells = <2>;
0893 };
0894
0895 };
0896
0897 mpu_cm: clock@8300 {
0898 compatible = "ti,omap4-cm";
0899 clock-output-names = "mpu_cm";
0900 reg = <0x8300 0x100>;
0901 #address-cells = <1>;
0902 #size-cells = <1>;
0903 ranges = <0 0x8300 0x100>;
0904
0905 mpu_clkctrl: clock@20 {
0906 compatible = "ti,clkctrl";
0907 clock-output-names = "mpu_clkctrl";
0908 reg = <0x20 0x4>;
0909 #clock-cells = <2>;
0910 };
0911 };
0912
0913 gfx_l3_cm: clock@8400 {
0914 compatible = "ti,omap4-cm";
0915 clock-output-names = "gfx_l3_cm";
0916 reg = <0x8400 0x100>;
0917 #address-cells = <1>;
0918 #size-cells = <1>;
0919 ranges = <0 0x8400 0x100>;
0920
0921 gfx_l3_clkctrl: clock@20 {
0922 compatible = "ti,clkctrl";
0923 clock-output-names = "gfx_l3_clkctrl";
0924 reg = <0x20 0x4>;
0925 #clock-cells = <2>;
0926 };
0927 };
0928
0929 l4_rtc_cm: clock@8500 {
0930 compatible = "ti,omap4-cm";
0931 clock-output-names = "l4_rtc_cm";
0932 reg = <0x8500 0x100>;
0933 #address-cells = <1>;
0934 #size-cells = <1>;
0935 ranges = <0 0x8500 0x100>;
0936
0937 l4_rtc_clkctrl: clock@20 {
0938 compatible = "ti,clkctrl";
0939 clock-output-names = "l4_rtc_clkctrl";
0940 reg = <0x20 0x4>;
0941 #clock-cells = <2>;
0942 };
0943 };
0944
0945 per_cm: clock@8800 {
0946 compatible = "ti,omap4-cm";
0947 clock-output-names = "per_cm";
0948 reg = <0x8800 0xc00>;
0949 #address-cells = <1>;
0950 #size-cells = <1>;
0951 ranges = <0 0x8800 0xc00>;
0952
0953 l3_clkctrl: clock@20 {
0954 compatible = "ti,clkctrl";
0955 clock-output-names = "l3_clkctrl";
0956 reg = <0x20 0x3c>, <0x78 0x2c>;
0957 #clock-cells = <2>;
0958 };
0959
0960 l3s_clkctrl: clock@68 {
0961 compatible = "ti,clkctrl";
0962 clock-output-names = "l3s_clkctrl";
0963 reg = <0x68 0xc>, <0x220 0x4c>;
0964 #clock-cells = <2>;
0965 };
0966
0967 pruss_ocp_clkctrl: clock@320 {
0968 compatible = "ti,clkctrl";
0969 clock-output-names = "pruss_ocp_clkctrl";
0970 reg = <0x320 0x4>;
0971 #clock-cells = <2>;
0972 };
0973
0974 l4ls_clkctrl: clock@420 {
0975 compatible = "ti,clkctrl";
0976 clock-output-names = "l4ls_clkctrl";
0977 reg = <0x420 0x1a4>;
0978 #clock-cells = <2>;
0979 };
0980
0981 emif_clkctrl: clock@720 {
0982 compatible = "ti,clkctrl";
0983 clock-output-names = "emif_clkctrl";
0984 reg = <0x720 0x4>;
0985 #clock-cells = <2>;
0986 };
0987
0988 dss_clkctrl: clock@a20 {
0989 compatible = "ti,clkctrl";
0990 clock-output-names = "dss_clkctrl";
0991 reg = <0xa20 0x4>;
0992 #clock-cells = <2>;
0993 };
0994
0995 cpsw_125mhz_clkctrl: clock@b20 {
0996 compatible = "ti,clkctrl";
0997 clock-output-names = "cpsw_125mhz_clkctrl";
0998 reg = <0xb20 0x4>;
0999 #clock-cells = <2>;
1000 };
1001
1002 };
1003 };
