0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for AM4372 SoC
0004 *
0005 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 #include <dt-bindings/bus/ti-sysc.h>
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/clock/am4.h>
0012
0013 / {
0014 compatible = "ti,am4372", "ti,am43";
0015 interrupt-parent = <&wakeupgen>;
0016 #address-cells = <1>;
0017 #size-cells = <1>;
0018 chosen { };
0019
0020 memory@0 {
0021 device_type = "memory";
0022 reg = <0 0>;
0023 };
0024
0025 aliases {
0026 i2c0 = &i2c0;
0027 i2c1 = &i2c1;
0028 i2c2 = &i2c2;
0029 serial0 = &uart0;
0030 serial1 = &uart1;
0031 serial2 = &uart2;
0032 serial3 = &uart3;
0033 serial4 = &uart4;
0034 serial5 = &uart5;
0035 ethernet0 = &cpsw_port1;
0036 ethernet1 = &cpsw_port2;
0037 spi0 = &qspi;
0038 };
0039
0040 cpus {
0041 #address-cells = <1>;
0042 #size-cells = <0>;
0043 cpu: cpu@0 {
0044 compatible = "arm,cortex-a9";
0045 enable-method = "ti,am4372";
0046 device_type = "cpu";
0047 reg = <0>;
0048
0049 clocks = <&dpll_mpu_ck>;
0050 clock-names = "cpu";
0051
0052 operating-points-v2 = <&cpu0_opp_table>;
0053
0054 clock-latency = <300000>; /* From omap-cpufreq driver */
0055 cpu-idle-states = <&mpu_gate>;
0056 };
0057
0058 idle-states {
0059 mpu_gate: mpu_gate {
0060 compatible = "arm,idle-state";
0061 entry-latency-us = <40>;
0062 exit-latency-us = <100>;
0063 min-residency-us = <300>;
0064 local-timer-stop;
0065 };
0066 };
0067 };
0068
0069 cpu0_opp_table: opp-table {
0070 compatible = "operating-points-v2-ti-cpu";
0071 syscon = <&scm_conf>;
0072
0073 opp50-300000000 {
0074 opp-hz = /bits/ 64 <300000000>;
0075 opp-microvolt = <950000 931000 969000>;
0076 opp-supported-hw = <0xFF 0x01>;
0077 opp-suspend;
0078 };
0079
0080 opp100-600000000 {
0081 opp-hz = /bits/ 64 <600000000>;
0082 opp-microvolt = <1100000 1078000 1122000>;
0083 opp-supported-hw = <0xFF 0x04>;
0084 };
0085
0086 opp120-720000000 {
0087 opp-hz = /bits/ 64 <720000000>;
0088 opp-microvolt = <1200000 1176000 1224000>;
0089 opp-supported-hw = <0xFF 0x08>;
0090 };
0091
0092 oppturbo-800000000 {
0093 opp-hz = /bits/ 64 <800000000>;
0094 opp-microvolt = <1260000 1234800 1285200>;
0095 opp-supported-hw = <0xFF 0x10>;
0096 };
0097
0098 oppnitro-1000000000 {
0099 opp-hz = /bits/ 64 <1000000000>;
0100 opp-microvolt = <1325000 1298500 1351500>;
0101 opp-supported-hw = <0xFF 0x20>;
0102 };
0103 };
0104
0105 soc {
0106 compatible = "ti,omap-infra";
0107 };
0108
0109 gic: interrupt-controller@48241000 {
0110 compatible = "arm,cortex-a9-gic";
0111 interrupt-controller;
0112 #interrupt-cells = <3>;
0113 reg = <0x48241000 0x1000>,
0114 <0x48240100 0x0100>;
0115 interrupt-parent = <&gic>;
0116 };
0117
0118 wakeupgen: interrupt-controller@48281000 {
0119 compatible = "ti,omap4-wugen-mpu";
0120 interrupt-controller;
0121 #interrupt-cells = <3>;
0122 reg = <0x48281000 0x1000>;
0123 interrupt-parent = <&gic>;
0124 };
0125
0126 scu: scu@48240000 {
0127 compatible = "arm,cortex-a9-scu";
0128 reg = <0x48240000 0x100>;
0129 };
0130
0131 global_timer: timer@48240200 {
0132 compatible = "arm,cortex-a9-global-timer";
0133 reg = <0x48240200 0x100>;
0134 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
0135 interrupt-parent = <&gic>;
0136 clocks = <&mpu_periphclk>;
0137 };
0138
0139 local_timer: timer@48240600 {
0140 compatible = "arm,cortex-a9-twd-timer";
0141 reg = <0x48240600 0x100>;
0142 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
0143 interrupt-parent = <&gic>;
0144 clocks = <&mpu_periphclk>;
0145 };
0146
0147 cache-controller@48242000 {
0148 compatible = "arm,pl310-cache";
0149 reg = <0x48242000 0x1000>;
0150 cache-unified;
0151 cache-level = <2>;
0152 };
0153
0154 ocp@44000000 {
0155 compatible = "simple-pm-bus";
0156 power-domains = <&prm_per>;
0157 clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>;
0158 clock-names = "fck";
0159 #address-cells = <1>;
0160 #size-cells = <1>;
0161 ranges;
0162 ti,no-idle;
0163
0164 l3-noc@44000000 {
0165 compatible = "ti,am4372-l3-noc";
0166 reg = <0x44000000 0x400000>,
0167 <0x44800000 0x400000>;
0168 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0169 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0170 };
0171
0172 l4_wkup: interconnect@44c00000 {
0173 };
0174 l4_per: interconnect@48000000 {
0175 };
0176 l4_fast: interconnect@4a000000 {
0177 };
0178
0179 target-module@4c000000 {
0180 compatible = "ti,sysc-omap4-simple", "ti,sysc";
0181 reg = <0x4c000000 0x4>;
0182 reg-names = "rev";
0183 clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
0184 clock-names = "fck";
0185 ti,no-idle;
0186 #address-cells = <1>;
0187 #size-cells = <1>;
0188 ranges = <0x0 0x4c000000 0x1000000>;
0189
0190 emif: emif@0 {
0191 compatible = "ti,emif-am4372";
0192 reg = <0 0x1000000>;
0193 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0194 sram = <&pm_sram_code
0195 &pm_sram_data>;
0196 };
0197 };
0198
0199 target-module@49000000 {
0200 compatible = "ti,sysc-omap4", "ti,sysc";
0201 reg = <0x49000000 0x4>;
0202 reg-names = "rev";
0203 clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
0204 clock-names = "fck";
0205 #address-cells = <1>;
0206 #size-cells = <1>;
0207 ranges = <0x0 0x49000000 0x10000>;
0208
0209 edma: dma@0 {
0210 compatible = "ti,edma3-tpcc";
0211 reg = <0 0x10000>;
0212 reg-names = "edma3_cc";
0213 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0214 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0215 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0216 interrupt-names = "edma3_ccint", "edma3_mperr",
0217 "edma3_ccerrint";
0218 dma-requests = <64>;
0219 #dma-cells = <2>;
0220
0221 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
0222 <&edma_tptc2 0>;
0223
0224 ti,edma-memcpy-channels = <58 59>;
0225 };
0226 };
0227
0228 target-module@49800000 {
0229 compatible = "ti,sysc-omap4", "ti,sysc";
0230 reg = <0x49800000 0x4>,
0231 <0x49800010 0x4>;
0232 reg-names = "rev", "sysc";
0233 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
0234 ti,sysc-midle = <SYSC_IDLE_FORCE>;
0235 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0236 <SYSC_IDLE_SMART>;
0237 clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
0238 clock-names = "fck";
0239 #address-cells = <1>;
0240 #size-cells = <1>;
0241 ranges = <0x0 0x49800000 0x100000>;
0242
0243 edma_tptc0: dma@0 {
0244 compatible = "ti,edma3-tptc";
0245 reg = <0 0x100000>;
0246 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
0247 interrupt-names = "edma3_tcerrint";
0248 };
0249 };
0250
0251 target-module@49900000 {
0252 compatible = "ti,sysc-omap4", "ti,sysc";
0253 reg = <0x49900000 0x4>,
0254 <0x49900010 0x4>;
0255 reg-names = "rev", "sysc";
0256 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
0257 ti,sysc-midle = <SYSC_IDLE_FORCE>;
0258 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0259 <SYSC_IDLE_SMART>;
0260 clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
0261 clock-names = "fck";
0262 #address-cells = <1>;
0263 #size-cells = <1>;
0264 ranges = <0x0 0x49900000 0x100000>;
0265
0266 edma_tptc1: dma@0 {
0267 compatible = "ti,edma3-tptc";
0268 reg = <0 0x100000>;
0269 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0270 interrupt-names = "edma3_tcerrint";
0271 };
0272 };
0273
0274 target-module@49a00000 {
0275 compatible = "ti,sysc-omap4", "ti,sysc";
0276 reg = <0x49a00000 0x4>,
0277 <0x49a00010 0x4>;
0278 reg-names = "rev", "sysc";
0279 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
0280 ti,sysc-midle = <SYSC_IDLE_FORCE>;
0281 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0282 <SYSC_IDLE_SMART>;
0283 clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
0284 clock-names = "fck";
0285 #address-cells = <1>;
0286 #size-cells = <1>;
0287 ranges = <0x0 0x49a00000 0x100000>;
0288
0289 edma_tptc2: dma@0 {
0290 compatible = "ti,edma3-tptc";
0291 reg = <0 0x100000>;
0292 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0293 interrupt-names = "edma3_tcerrint";
0294 };
0295 };
0296
0297 target-module@47810000 {
0298 compatible = "ti,sysc-omap2", "ti,sysc";
0299 reg = <0x478102fc 0x4>,
0300 <0x47810110 0x4>,
0301 <0x47810114 0x4>;
0302 reg-names = "rev", "sysc", "syss";
0303 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0304 SYSC_OMAP2_ENAWAKEUP |
0305 SYSC_OMAP2_SOFTRESET |
0306 SYSC_OMAP2_AUTOIDLE)>;
0307 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0308 <SYSC_IDLE_NO>,
0309 <SYSC_IDLE_SMART>;
0310 ti,syss-mask = <1>;
0311 clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
0312 clock-names = "fck";
0313 #address-cells = <1>;
0314 #size-cells = <1>;
0315 ranges = <0x0 0x47810000 0x1000>;
0316
0317 mmc3: mmc@0 {
0318 compatible = "ti,am437-sdhci";
0319 ti,needs-special-reset;
0320 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0321 reg = <0x0 0x1000>;
0322 status = "disabled";
0323 };
0324 };
0325
0326 sham_target: target-module@53100000 {
0327 compatible = "ti,sysc-omap3-sham", "ti,sysc";
0328 reg = <0x53100100 0x4>,
0329 <0x53100110 0x4>,
0330 <0x53100114 0x4>;
0331 reg-names = "rev", "sysc", "syss";
0332 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
0333 SYSC_OMAP2_AUTOIDLE)>;
0334 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0335 <SYSC_IDLE_NO>,
0336 <SYSC_IDLE_SMART>;
0337 ti,syss-mask = <1>;
0338 /* Domains (P, C): per_pwrdm, l3_clkdm */
0339 clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
0340 clock-names = "fck";
0341 #address-cells = <1>;
0342 #size-cells = <1>;
0343 ranges = <0x0 0x53100000 0x1000>;
0344
0345 sham: sham@0 {
0346 compatible = "ti,omap5-sham";
0347 reg = <0 0x300>;
0348 dmas = <&edma 36 0>;
0349 dma-names = "rx";
0350 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0351 };
0352 };
0353
0354 aes_target: target-module@53501000 {
0355 compatible = "ti,sysc-omap2", "ti,sysc";
0356 reg = <0x53501080 0x4>,
0357 <0x53501084 0x4>,
0358 <0x53501088 0x4>;
0359 reg-names = "rev", "sysc", "syss";
0360 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
0361 SYSC_OMAP2_AUTOIDLE)>;
0362 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0363 <SYSC_IDLE_NO>,
0364 <SYSC_IDLE_SMART>,
0365 <SYSC_IDLE_SMART_WKUP>;
0366 ti,syss-mask = <1>;
0367 /* Domains (P, C): per_pwrdm, l3_clkdm */
0368 clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
0369 clock-names = "fck";
0370 #address-cells = <1>;
0371 #size-cells = <1>;
0372 ranges = <0x0 0x53501000 0x1000>;
0373
0374 aes: aes@0 {
0375 compatible = "ti,omap4-aes";
0376 reg = <0 0xa0>;
0377 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0378 dmas = <&edma 6 0>,
0379 <&edma 5 0>;
0380 dma-names = "tx", "rx";
0381 };
0382 };
0383
0384 des_target: target-module@53701000 {
0385 compatible = "ti,sysc-omap2", "ti,sysc";
0386 reg = <0x53701030 0x4>,
0387 <0x53701034 0x4>,
0388 <0x53701038 0x4>;
0389 reg-names = "rev", "sysc", "syss";
0390 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
0391 SYSC_OMAP2_AUTOIDLE)>;
0392 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0393 <SYSC_IDLE_NO>,
0394 <SYSC_IDLE_SMART>,
0395 <SYSC_IDLE_SMART_WKUP>;
0396 ti,syss-mask = <1>;
0397 /* Domains (P, C): per_pwrdm, l3_clkdm */
0398 clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
0399 clock-names = "fck";
0400 #address-cells = <1>;
0401 #size-cells = <1>;
0402 ranges = <0 0x53701000 0x1000>;
0403
0404 des: des@0 {
0405 compatible = "ti,omap4-des";
0406 reg = <0 0xa0>;
0407 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
0408 dmas = <&edma 34 0>,
0409 <&edma 33 0>;
0410 dma-names = "tx", "rx";
0411 };
0412 };
0413
0414 pruss_tm: target-module@54400000 {
0415 compatible = "ti,sysc-pruss", "ti,sysc";
0416 reg = <0x54426000 0x4>,
0417 <0x54426004 0x4>;
0418 reg-names = "rev", "sysc";
0419 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
0420 SYSC_PRUSS_SUB_MWAIT)>;
0421 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0422 <SYSC_IDLE_NO>,
0423 <SYSC_IDLE_SMART>;
0424 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0425 <SYSC_IDLE_NO>,
0426 <SYSC_IDLE_SMART>;
0427 clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
0428 clock-names = "fck";
0429 resets = <&prm_per 1>;
0430 reset-names = "rstctrl";
0431 #address-cells = <1>;
0432 #size-cells = <1>;
0433 ranges = <0x0 0x54400000 0x80000>;
0434
0435 pruss1: pruss@0 {
0436 compatible = "ti,am4376-pruss1";
0437 reg = <0x0 0x40000>;
0438 #address-cells = <1>;
0439 #size-cells = <1>;
0440 ranges;
0441
0442 pruss1_mem: memories@0 {
0443 reg = <0x0 0x2000>,
0444 <0x2000 0x2000>,
0445 <0x10000 0x8000>;
0446 reg-names = "dram0", "dram1",
0447 "shrdram2";
0448 };
0449
0450 pruss1_cfg: cfg@26000 {
0451 compatible = "ti,pruss-cfg", "syscon";
0452 reg = <0x26000 0x2000>;
0453 #address-cells = <1>;
0454 #size-cells = <1>;
0455 ranges = <0x0 0x26000 0x2000>;
0456
0457 clocks {
0458 #address-cells = <1>;
0459 #size-cells = <0>;
0460
0461 pruss1_iepclk_mux: iepclk-mux@30 {
0462 reg = <0x30>;
0463 #clock-cells = <0>;
0464 clocks = <&sysclk_div>, /* icss_iep_gclk */
0465 <&pruss_ocp_gclk>; /* icss_ocp_gclk */
0466 };
0467 };
0468 };
0469
0470 pruss1_mii_rt: mii-rt@32000 {
0471 compatible = "ti,pruss-mii", "syscon";
0472 reg = <0x32000 0x58>;
0473 };
0474
0475 pruss1_intc: interrupt-controller@20000 {
0476 compatible = "ti,pruss-intc";
0477 reg = <0x20000 0x2000>;
0478 interrupt-controller;
0479 #interrupt-cells = <3>;
0480 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
0481 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
0482 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0483 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
0484 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
0485 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
0486 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0487 interrupt-names = "host_intr0", "host_intr1",
0488 "host_intr2", "host_intr3",
0489 "host_intr4",
0490 "host_intr6", "host_intr7";
0491 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
0492 };
0493
0494 pru1_0: pru@34000 {
0495 compatible = "ti,am4376-pru";
0496 reg = <0x34000 0x3000>,
0497 <0x22000 0x400>,
0498 <0x22400 0x100>;
0499 reg-names = "iram", "control", "debug";
0500 firmware-name = "am437x-pru1_0-fw";
0501 };
0502
0503 pru1_1: pru@38000 {
0504 compatible = "ti,am4376-pru";
0505 reg = <0x38000 0x3000>,
0506 <0x24000 0x400>,
0507 <0x24400 0x100>;
0508 reg-names = "iram", "control", "debug";
0509 firmware-name = "am437x-pru1_1-fw";
0510 };
0511
0512 pruss1_mdio: mdio@32400 {
0513 compatible = "ti,davinci_mdio";
0514 reg = <0x32400 0x90>;
0515 clocks = <&dpll_core_m4_ck>;
0516 clock-names = "fck";
0517 bus_freq = <1000000>;
0518 #address-cells = <1>;
0519 #size-cells = <0>;
0520 };
0521 };
0522
0523 pruss0: pruss@40000 {
0524 compatible = "ti,am4376-pruss0";
0525 reg = <0x40000 0x40000>;
0526 #address-cells = <1>;
0527 #size-cells = <1>;
0528 ranges;
0529
0530 pruss0_mem: memories@40000 {
0531 reg = <0x40000 0x1000>,
0532 <0x42000 0x1000>;
0533 reg-names = "dram0", "dram1";
0534 };
0535
0536 pruss0_cfg: cfg@66000 {
0537 compatible = "ti,pruss-cfg", "syscon";
0538 reg = <0x66000 0x2000>;
0539 #address-cells = <1>;
0540 #size-cells = <1>;
0541 ranges = <0x0 0x66000 0x2000>;
0542
0543 clocks {
0544 #address-cells = <1>;
0545 #size-cells = <0>;
0546
0547 pruss0_iepclk_mux: iepclk-mux@30 {
0548 reg = <0x30>;
0549 #clock-cells = <0>;
0550 clocks = <&sysclk_div>, /* icss_iep_gclk */
0551 <&pruss_ocp_gclk>; /* icss_ocp_gclk */
0552 };
0553 };
0554 };
0555
0556 pruss0_mii_rt: mii-rt@72000 {
0557 compatible = "ti,pruss-mii", "syscon";
0558 reg = <0x72000 0x58>;
0559 status = "disabled";
0560 };
0561
0562 pruss0_intc: interrupt-controller@60000 {
0563 compatible = "ti,pruss-intc";
0564 reg = <0x60000 0x2000>;
0565 interrupt-controller;
0566 #interrupt-cells = <3>;
0567 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
0568 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
0569 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
0570 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
0571 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
0572 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
0573 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
0574 interrupt-names = "host_intr0", "host_intr1",
0575 "host_intr2", "host_intr3",
0576 "host_intr4",
0577 "host_intr6", "host_intr7";
0578 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
0579 };
0580
0581 pru0_0: pru@74000 {
0582 compatible = "ti,am4376-pru";
0583 reg = <0x74000 0x1000>,
0584 <0x62000 0x400>,
0585 <0x62400 0x100>;
0586 reg-names = "iram", "control", "debug";
0587 firmware-name = "am437x-pru0_0-fw";
0588 };
0589
0590 pru0_1: pru@78000 {
0591 compatible = "ti,am4376-pru";
0592 reg = <0x78000 0x1000>,
0593 <0x64000 0x400>,
0594 <0x64400 0x100>;
0595 reg-names = "iram", "control", "debug";
0596 firmware-name = "am437x-pru0_1-fw";
0597 };
0598 };
0599 };
0600
0601 target-module@50000000 {
0602 compatible = "ti,sysc-omap2", "ti,sysc";
0603 reg = <0x50000000 4>,
0604 <0x50000010 4>,
0605 <0x50000014 4>;
0606 reg-names = "rev", "sysc", "syss";
0607 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0608 <SYSC_IDLE_NO>,
0609 <SYSC_IDLE_SMART>;
0610 ti,syss-mask = <1>;
0611 clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;
0612 clock-names = "fck";
0613 #address-cells = <1>;
0614 #size-cells = <1>;
0615 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
0616 <0x00000000 0x00000000 0x40000000>; /* data */
0617
0618 gpmc: gpmc@50000000 {
0619 compatible = "ti,am3352-gpmc";
0620 dmas = <&edma 52 0>;
0621 dma-names = "rxtx";
0622 clocks = <&l3s_gclk>;
0623 clock-names = "fck";
0624 reg = <0x50000000 0x2000>;
0625 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0626 gpmc,num-cs = <7>;
0627 gpmc,num-waitpins = <2>;
0628 #address-cells = <2>;
0629 #size-cells = <1>;
0630 interrupt-controller;
0631 #interrupt-cells = <2>;
0632 gpio-controller;
0633 #gpio-cells = <2>;
0634 status = "disabled";
0635 };
0636 };
0637
0638 target-module@47900000 {
0639 compatible = "ti,sysc-omap4", "ti,sysc";
0640 reg = <0x47900000 0x4>,
0641 <0x47900010 0x4>;
0642 reg-names = "rev", "sysc";
0643 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0644 <SYSC_IDLE_NO>,
0645 <SYSC_IDLE_SMART>,
0646 <SYSC_IDLE_SMART_WKUP>;
0647 clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
0648 clock-names = "fck";
0649 #address-cells = <1>;
0650 #size-cells = <1>;
0651 ranges = <0x0 0x47900000 0x1000>,
0652 <0x30000000 0x30000000 0x4000000>;
0653
0654 qspi: spi@0 {
0655 compatible = "ti,am4372-qspi";
0656 reg = <0 0x100>,
0657 <0x30000000 0x4000000>;
0658 reg-names = "qspi_base", "qspi_mmap";
0659 clocks = <&dpll_per_m2_div4_ck>;
0660 clock-names = "fck";
0661 #address-cells = <1>;
0662 #size-cells = <0>;
0663 interrupts = <0 138 0x4>;
0664 num-cs = <4>;
0665 };
0666 };
0667
0668 target-module@40300000 {
0669 compatible = "ti,sysc-omap4-simple", "ti,sysc";
0670 clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>;
0671 clock-names = "fck";
0672 ti,no-idle;
0673 #address-cells = <1>;
0674 #size-cells = <1>;
0675 ranges = <0 0x40300000 0x40000>;
0676
0677 ocmcram: sram@0 {
0678 compatible = "mmio-sram";
0679 reg = <0 0x40000>; /* 256k */
0680 ranges = <0 0 0x40000>;
0681 #address-cells = <1>;
0682 #size-cells = <1>;
0683
0684 pm_sram_code: pm-code-sram@0 {
0685 compatible = "ti,sram";
0686 reg = <0x0 0x1000>;
0687 protect-exec;
0688 };
0689
0690 pm_sram_data: pm-data-sram@1000 {
0691 compatible = "ti,sram";
0692 reg = <0x1000 0x1000>;
0693 pool;
0694 };
0695 };
0696 };
0697
0698 target-module@56000000 {
0699 compatible = "ti,sysc-omap4", "ti,sysc";
0700 reg = <0x5600fe00 0x4>,
0701 <0x5600fe10 0x4>;
0702 reg-names = "rev", "sysc";
0703 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0704 <SYSC_IDLE_NO>,
0705 <SYSC_IDLE_SMART>;
0706 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0707 <SYSC_IDLE_NO>,
0708 <SYSC_IDLE_SMART>;
0709 clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
0710 clock-names = "fck";
0711 power-domains = <&prm_gfx>;
0712 resets = <&prm_gfx 0>;
0713 reset-names = "rstctrl";
0714 #address-cells = <1>;
0715 #size-cells = <1>;
0716 ranges = <0 0x56000000 0x1000000>;
0717 };
0718 };
0719 };
0720
0721 #include "am437x-l4.dtsi"
0722 #include "am43xx-clocks.dtsi"
0723
0724 &prcm {
0725 prm_mpu: prm@300 {
0726 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
0727 reg = <0x300 0x100>;
0728 #power-domain-cells = <0>;
0729 };
0730
0731 prm_gfx: prm@400 {
0732 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
0733 reg = <0x400 0x100>;
0734 #power-domain-cells = <0>;
0735 #reset-cells = <1>;
0736 };
0737
0738 prm_rtc: prm@500 {
0739 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
0740 reg = <0x500 0x100>;
0741 #power-domain-cells = <0>;
0742 };
0743
0744 prm_tamper: prm@600 {
0745 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
0746 reg = <0x600 0x100>;
0747 #power-domain-cells = <0>;
0748 };
0749
0750 prm_cefuse: prm@700 {
0751 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
0752 reg = <0x700 0x100>;
0753 #power-domain-cells = <0>;
0754 };
0755
0756 prm_per: prm@800 {
0757 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
0758 reg = <0x800 0x100>;
0759 #reset-cells = <1>;
0760 #power-domain-cells = <0>;
0761 };
0762
0763 prm_wkup: prm@2000 {
0764 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
0765 reg = <0x2000 0x100>;
0766 #reset-cells = <1>;
0767 #power-domain-cells = <0>;
0768 };
0769
0770 prm_device: prm@4000 {
0771 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
0772 reg = <0x4000 0x100>;
0773 #reset-cells = <1>;
0774 };
0775 };
0776
0777 /* Preferred always-on timer for clocksource */
0778 &timer1_target {
0779 ti,no-reset-on-init;
0780 ti,no-idle;
0781 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>,
0782 <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
0783 clock-names = "fck", "ick";
0784 timer@0 {
0785 assigned-clocks = <&timer1_fck>;
0786 assigned-clock-parents = <&sys_clkin_ck>;
0787 };
0788 };
0789
0790 /* Preferred timer for clockevent */
0791 &timer2_target {
0792 ti,no-reset-on-init;
0793 ti,no-idle;
0794 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>,
0795 <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
0796 clock-names = "fck", "ick";
0797 timer@0 {
0798 assigned-clocks = <&timer2_fck>;
0799 assigned-clock-parents = <&sys_clkin_ck>;
0800 };
0801 };
