0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device tree for Winterland IceBoard
0004 *
0005 * https://mcgillcosmology.com
0006 * https://threespeedlogic.com
0007 *
0008 * This is an ARM + FPGA instrumentation board used at telescopes in
0009 * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO
0010 * observatory in British Columbia (CHIME).
0011 *
0012 * Copyright (c) 2019 Three-Speed Logic, Inc. <gsmecher@threespeedlogic.com>
0013 */
0014
0015 /dts-v1/;
0016
0017 #include "dm814x.dtsi"
0018 #include <dt-bindings/interrupt-controller/irq.h>
0019
0020 / {
0021 model = "Winterland IceBoard";
0022 compatible = "ti,dm8148", "ti,dm814";
0023
0024 chosen {
0025 stdout-path = "serial1:115200n8";
0026 bootargs = "earlycon";
0027 };
0028
0029 memory@80000000 {
0030 device_type = "memory";
0031 reg = <0x80000000 0x40000000>; /* 1 GB */
0032 };
0033
0034 vmmcsd_fixed: fixedregulator0 {
0035 compatible = "regulator-fixed";
0036 regulator-name = "vmmcsd_fixed";
0037 regulator-min-microvolt = <3300000>;
0038 regulator-max-microvolt = <3300000>;
0039 regulator-always-on;
0040 };
0041 };
0042
0043 /* The MAC provides internal delay for the transmit path ONLY, which is enabled
0044 * provided no -id/-txid/-rxid suffix is provided to "phy-mode".
0045 *
0046 * The receive path is delayed at the PHY. The recommended register settings
0047 * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the
0048 * conversion code in the kernel lies: the PHY's registers are 120 ps per tap,
0049 * and the kernel assumes 200 ps per tap. So we have fudged the numbers here to
0050 * obtain the correct register settings.
0051 */
0052 &mac { dual_emac = <1>; };
0053 &cpsw_emac0 {
0054 phy-handle = <ðphy0>;
0055 phy-mode = "rgmii";
0056 dual_emac_res_vlan = <1>;
0057 };
0058 &cpsw_emac1 {
0059 phy-handle = <ðphy1>;
0060 phy-mode = "rgmii";
0061 dual_emac_res_vlan = <2>;
0062 };
0063
0064 &davinci_mdio {
0065 ethphy0: ethernet-phy@0 {
0066 reg = <0x2>;
0067
0068 rxc-skew-ps = <3000>;
0069 rxdv-skew-ps = <0>;
0070
0071 rxd3-skew-ps = <0>;
0072 rxd2-skew-ps = <0>;
0073 rxd1-skew-ps = <0>;
0074 rxd0-skew-ps = <0>;
0075
0076 phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
0077 };
0078
0079 ethphy1: ethernet-phy@1 {
0080 reg = <0x1>;
0081
0082 rxc-skew-ps = <3000>;
0083 rxdv-skew-ps = <0>;
0084
0085 rxd3-skew-ps = <0>;
0086 rxd2-skew-ps = <0>;
0087 rxd1-skew-ps = <0>;
0088 rxd0-skew-ps = <0>;
0089
0090 phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
0091 };
0092 };
0093
0094 &mmc1 { status = "disabled"; };
0095 &mmc2 {
0096 pinctrl-names = "default";
0097 pinctrl-0 = <&mmc2_pins>;
0098 vmmc-supply = <&vmmcsd_fixed>;
0099 bus-width = <4>;
0100 };
0101 &mmc3 { status = "disabled"; };
0102
0103 &i2c1 {
0104 /* Most I2C activity happens through this port, with the sole exception
0105 * of the backplane. Since there are multiply assigned addresses, the
0106 * "i2c-mux-idle-disconnect" is important.
0107 */
0108
0109 pca9548@70 {
0110 compatible = "nxp,pca9548";
0111 reg = <0x70>;
0112 #address-cells = <1>;
0113 #size-cells = <0>;
0114 i2c-mux-idle-disconnect;
0115
0116 i2c@0 {
0117 /* FMC A */
0118 #address-cells = <1>;
0119 #size-cells = <0>;
0120 reg = <0>;
0121 };
0122
0123 i2c@1 {
0124 /* FMC B */
0125 #address-cells = <1>;
0126 #size-cells = <0>;
0127 reg = <1>;
0128 };
0129
0130 i2c@2 {
0131 /* QSFP A */
0132 #address-cells = <1>;
0133 #size-cells = <0>;
0134 reg = <2>;
0135 };
0136
0137 i2c@3 {
0138 /* QSFP B */
0139 #address-cells = <1>;
0140 #size-cells = <0>;
0141 reg = <3>;
0142 };
0143
0144 i2c@4 {
0145 /* SFP */
0146 #address-cells = <1>;
0147 #size-cells = <0>;
0148 reg = <4>;
0149 };
0150
0151 i2c@5 {
0152 #address-cells = <1>;
0153 #size-cells = <0>;
0154 reg = <5>;
0155
0156 ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; };
0157 ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; };
0158 ina230@42 { compatible = "ti,ina230"; reg = <0x42>; shunt-resistor = <5000>; };
0159
0160 ina230@44 { compatible = "ti,ina230"; reg = <0x44>; shunt-resistor = <5000>; };
0161 ina230@45 { compatible = "ti,ina230"; reg = <0x45>; shunt-resistor = <5000>; };
0162 ina230@46 { compatible = "ti,ina230"; reg = <0x46>; shunt-resistor = <5000>; };
0163
0164 ina230@47 { compatible = "ti,ina230"; reg = <0x47>; shunt-resistor = <5500>; };
0165 ina230@48 { compatible = "ti,ina230"; reg = <0x48>; shunt-resistor = <2360>; };
0166 ina230@49 { compatible = "ti,ina230"; reg = <0x49>; shunt-resistor = <2360>; };
0167 ina230@43 { compatible = "ti,ina230"; reg = <0x43>; shunt-resistor = <2360>; };
0168 ina230@4b { compatible = "ti,ina230"; reg = <0x4b>; shunt-resistor = <5500>; };
0169 ina230@4c { compatible = "ti,ina230"; reg = <0x4c>; shunt-resistor = <2360>; };
0170 ina230@4d { compatible = "ti,ina230"; reg = <0x4d>; shunt-resistor = <770>; };
0171 ina230@4e { compatible = "ti,ina230"; reg = <0x4e>; shunt-resistor = <770>; };
0172 ina230@4f { compatible = "ti,ina230"; reg = <0x4f>; shunt-resistor = <770>; };
0173 };
0174
0175 i2c@6 {
0176 /* Backplane */
0177 #address-cells = <1>;
0178 #size-cells = <0>;
0179 reg = <6>;
0180 };
0181
0182 i2c@7 {
0183 #address-cells = <1>;
0184 #size-cells = <0>;
0185 reg = <7>;
0186
0187 u41: pca9575@20 {
0188 compatible = "nxp,pca9575";
0189 reg = <0x20>;
0190 gpio-controller;
0191 #gpio-cells = <2>;
0192
0193 gpio-line-names =
0194 "FMCA_EN_12V0", "FMCA_EN_3V3", "FMCA_EN_VADJ", "FMCA_PG_M2C",
0195 "FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS",
0196 "FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C",
0197 "FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL";
0198 reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
0199 };
0200
0201 u42: pca9575@21 {
0202 compatible = "nxp,pca9575";
0203 reg = <0x21>;
0204 gpio-controller;
0205 #gpio-cells = <2>;
0206 gpio-line-names =
0207 "QSFPA_ModPrsL", "QSFPA_IntL", "QSFPA_ResetL", "QSFPA_ModSelL",
0208 "QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL",
0209 "SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1",
0210 "QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR";
0211 reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
0212 };
0213
0214 u48: pca9575@22 {
0215 compatible = "nxp,pca9575";
0216 reg = <0x22>;
0217 gpio-controller;
0218 #gpio-cells = <2>;
0219
0220 sw-gpios = <&u48 0 0>, <&u48 1 0>, <&u48 2 0>, <&u48 3 0>,
0221 <&u48 4 0>, <&u48 5 0>, <&u48 6 0>, <&u48 7 0>;
0222 led-gpios = <&u48 7 0>, <&u48 6 0>, <&u48 5 0>, <&u48 4 0>,
0223 <&u48 3 0>, <&u48 2 0>, <&u48 1 0>, <&u48 0 0>;
0224
0225 gpio-line-names =
0226 "GP_SW1", "GP_SW2", "GP_SW3", "GP_SW4",
0227 "GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8",
0228 "GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5",
0229 "GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1";
0230 reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
0231 };
0232
0233 u59: pca9575@23 {
0234 compatible = "nxp,pca9575";
0235 reg = <0x23>;
0236 gpio-controller;
0237 #gpio-cells = <2>;
0238 gpio-line-names =
0239 "GP_LED9", "GP_LED10", "GP_LED11", "GP_LED12",
0240 "GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault",
0241 "BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3",
0242 "BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17";
0243 reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
0244 };
0245
0246 tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; };
0247 tmp100@4a { compatible = "ti,tmp100"; reg = <0x4a>; };
0248 tmp100@4b { compatible = "ti,tmp100"; reg = <0x4b>; };
0249 tmp100@4c { compatible = "ti,tmp100"; reg = <0x4c>; };
0250
0251 /* EEPROM bank and serial number are treated as separate devices */
0252 at24c01@57 { compatible = "atmel,24c01"; reg = <0x57>; };
0253 at24cs01@5f { compatible = "atmel,24cs01"; reg = <0x5f>; };
0254 };
0255 };
0256 };
0257
0258 &i2c2 {
0259 pca9548@71 {
0260 compatible = "nxp,pca9548";
0261 reg = <0x71>;
0262 #address-cells = <1>;
0263 #size-cells = <0>;
0264
0265 i2c@6 {
0266 /* Backplane */
0267 #address-cells = <1>;
0268 #size-cells = <0>;
0269 reg = <6>;
0270 multi-master;
0271
0272 /* All backplanes should have this -- it's how we know they're there. */
0273 at24c08@54 { compatible="atmel,24c08"; reg=<0x54>; };
0274 at24cs08@5c { compatible="atmel,24cs08"; reg=<0x5c>; };
0275
0276 /* 16 slot backplane */
0277 tmp421@4d { compatible="ti,tmp421"; reg=<0x4d>; };
0278 tmp421@4e { compatible="ti,tmp421"; reg=<0x4e>; };
0279 ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <2360>; };
0280 amc6821@18 { compatible = "ti,amc6821"; reg = <0x18>; };
0281
0282 /* Single slot backplane */
0283 };
0284 };
0285 };
0286
0287 &pincntl {
0288 mmc2_pins: pinmux_mmc2_pins {
0289 pinctrl-single,pins = <
0290 DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */
0291 DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */
0292 DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */
0293 DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */
0294 DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */
0295 DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */
0296 DM814X_IOPAD(0x0924, PIN_INPUT_PULLUP | 0x40) /* SD1_POW */
0297 DM814X_IOPAD(0x0928, PIN_INPUT | 0x40) /* SD1_SDWP */
0298 DM814X_IOPAD(0x093C, PIN_INPUT | 0x2) /* SD1_SDCD */
0299 >;
0300 };
0301
0302 usb0_pins: pinmux_usb0_pins {
0303 pinctrl-single,pins = <
0304 DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */
0305 >;
0306 };
0307
0308 usb1_pins: pinmux_usb1_pins {
0309 pinctrl-single,pins = <
0310 DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */
0311 >;
0312 };
0313
0314 gpio1_pins: pinmux_gpio1_pins {
0315 pinctrl-single,pins = <
0316 DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */
0317 DM814X_IOPAD(0x0820, PIN_INPUT | 0x80) /* INIT_B */
0318 DM814X_IOPAD(0x0824, PIN_INPUT | 0x80) /* DONE */
0319
0320 DM814X_IOPAD(0x0838, PIN_INPUT_PULLUP | 0x80) /* FMCA_TMS */
0321 DM814X_IOPAD(0x083c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TCK */
0322 DM814X_IOPAD(0x0898, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDO */
0323 DM814X_IOPAD(0x089c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDI */
0324 DM814X_IOPAD(0x08ac, PIN_INPUT_PULLUP | 0x80) /* FMCA_TRST */
0325
0326 DM814X_IOPAD(0x08b0, PIN_INPUT_PULLUP | 0x80) /* FMCB_TMS */
0327 DM814X_IOPAD(0x0a88, PIN_INPUT_PULLUP | 0x80) /* FMCB_TCK */
0328 DM814X_IOPAD(0x0a8c, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDO */
0329 DM814X_IOPAD(0x08bc, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDI */
0330 DM814X_IOPAD(0x0a94, PIN_INPUT_PULLUP | 0x80) /* FMCB_TRST */
0331
0332 DM814X_IOPAD(0x08d4, PIN_INPUT_PULLUP | 0x80) /* FPGA_TMS */
0333 DM814X_IOPAD(0x0aa8, PIN_INPUT_PULLUP | 0x80) /* FPGA_TCK */
0334 DM814X_IOPAD(0x0adc, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDO */
0335 DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */
0336 >;
0337 };
0338
0339 gpio2_pins: pinmux_gpio2_pins {
0340 pinctrl-single,pins = <
0341 DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */
0342 DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */
0343 DM814X_IOPAD(0x08f4, PIN_INPUT_PULLUP | 0x80) /* PHY B IRQ */
0344 DM814X_IOPAD(0x08f8, PIN_INPUT_PULLUP | 0x80) /* PHY B RESET */
0345
0346 //DM814X_IOPAD(0x0a14, PIN_INPUT_PULLUP | 0x80) /* ARM IRQ */
0347 //DM814X_IOPAD(0x0900, PIN_INPUT | 0x80) /* GPIO IRQ */
0348 DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */
0349 >;
0350 };
0351
0352 gpio4_pins: pinmux_gpio4_pins {
0353 pinctrl-single,pins = <
0354 /* The PLL doesn't react well to the SPI controller reset, so
0355 * we force the CS lines to pull up as GPIOs until we're ready.
0356 * See https://e2e.ti.com/support/processors/f/791/t/276011?Linux-support-for-AM3874-DM8148-in-Arago-linux-omap3
0357 */
0358 DM814X_IOPAD(0x0b3c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO0 */
0359 DM814X_IOPAD(0x0b40, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO1 */
0360 DM814X_IOPAD(0x0b44, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO2 */
0361 DM814X_IOPAD(0x0b48, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO3 */
0362 DM814X_IOPAD(0x0b4c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO4 */
0363 DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */
0364 >;
0365 };
0366
0367 spi2_pins: pinmux_spi2_pins {
0368 pinctrl-single,pins = <
0369 DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */
0370 DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */
0371 >;
0372 };
0373
0374 spi4_pins: pinmux_spi4_pins {
0375 pinctrl-single,pins = <
0376 DM814X_IOPAD(0x0a7c, 0x20)
0377 DM814X_IOPAD(0x0b74, 0x20)
0378 DM814X_IOPAD(0x0b78, PIN_OUTPUT | 0x20)
0379 DM814X_IOPAD(0x0b7c, PIN_OUTPUT_PULLDOWN | 0x20)
0380 DM814X_IOPAD(0x0b80, PIN_INPUT | 0x20)
0381 >;
0382 };
0383 };
0384
0385 &gpio1 {
0386 pinctrl-names = "default";
0387 pinctrl-0 = <&gpio1_pins>;
0388 gpio-line-names =
0389 "", "PROGRAM_B", "INIT_B", "DONE", /* 0-3 */
0390 "", "", "", "", /* 4-7 */
0391 "FMCA_TMS", "FMCA_TCK", "FMCA_TDO", "FMCA_TDI", /* 8-11 */
0392 "", "", "", "FMCA_TRST", /* 12-15 */
0393 "FMCB_TMS", "FMCB_TCK", "FMCB_TDO", "FMCB_TDI", /* 16-19 */
0394 "FMCB_TRST", "", "", "", /* 20-23 */
0395 "FPGA_TMS", "FPGA_TCK", "FPGA_TDO", "FPGA_TDI", /* 24-27 */
0396 "", "", "", ""; /* 28-31 */
0397 };
0398
0399 &gpio2 {
0400 pinctrl-names = "default";
0401 pinctrl-0 = <&gpio2_pins>;
0402 gpio-line-names =
0403 "PHYA_IRQ_N", "PHYA_RESET_N", "", "", /* 0-3 */
0404 "", "", "", "PHYB_IRQ_N", /* 4-7 */
0405 "PHYB_RESET_N", "ARM_IRQ", "GPIO_IRQ", ""; /* 8-11 */
0406 };
0407
0408 &gpio3 {
0409 pinctrl-names = "default";
0410 /*pinctrl-0 = <&gpio3_pins>;*/
0411 gpio-line-names =
0412 "", "", "ARMClkSel0", "", /* 0-3 */
0413 "EnFPGARef", "", "", "ARMClkSel1"; /* 4-7 */
0414 };
0415
0416 &gpio4 {
0417 pinctrl-names = "default";
0418 pinctrl-0 = <&gpio4_pins>;
0419 gpio-line-names =
0420 "BP_ARM_GPIO0", "BP_ARM_GPIO1", "BP_ARM_GPIO2", "BP_ARM_GPIO3",
0421 "BP_ARM_GPIO4", "BP_ARM_GPIO5";
0422 };
0423
0424 &usb0 {
0425 pinctrl-names = "default";
0426 pinctrl-0 = <&usb0_pins>;
0427 dr_mode = "host";
0428 };
0429
0430 &usb1 {
0431 pinctrl-names = "default";
0432 pinctrl-0 = <&usb1_pins>;
0433 dr_mode = "host";
0434 };
0435
0436 &mcspi1 {
0437 flash@0 {
0438 #address-cells = <1>;
0439 #size-cells = <1>;
0440 compatible = "jedec,spi-nor";
0441 reg = <0>;
0442 spi-max-frequency = <40000000>;
0443
0444 fsbl@0 {
0445 /* 256 kB */
0446 label = "U-Boot-min";
0447 reg = <0 0x40000>;
0448 };
0449 ssbl@1 {
0450 /* 512 kB */
0451 label = "U-Boot";
0452 reg = <0x40000 0x80000>;
0453 };
0454 bootenv@2 {
0455 /* 256 kB */
0456 label = "U-Boot Env";
0457 reg = <0xc0000 0x40000>;
0458 };
0459 kernel@3 {
0460 /* 4 MB */
0461 label = "Kernel";
0462 reg = <0x100000 0x400000>;
0463 };
0464 ipmi@4 {
0465 label = "IPMI FRU";
0466 reg = <0x500000 0x40000>;
0467 };
0468 fs@5 {
0469 label = "File System";
0470 reg = <0x540000 0x1ac0000>;
0471 };
0472 };
0473 };
0474
0475 &mcspi3 {
0476 /* DMA event numbers stolen from MCASP */
0477 dmas = <&edma_xbar 8 0 16 &edma_xbar 9 0 17
0478 &edma_xbar 10 0 18 &edma_xbar 11 0 19>;
0479 dma-names = "tx0", "rx0", "tx1", "rx1";
0480 };
0481
0482 &mcspi4 {
0483 pinctrl-names = "default";
0484 pinctrl-0 = <&spi4_pins>;
0485
0486 /* DMA event numbers stolen from MCASP, MCBSP */
0487 dmas = <&edma_xbar 12 0 20 &edma_xbar 13 0 21>;
0488 dma-names = "tx0", "rx0";
0489 };
