0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP3 clock data
0004 *
0005 * Copyright (C) 2013 Texas Instruments, Inc.
0006 */
0007 &scm_clocks {
0008 emac_ick: emac_ick@32c {
0009 #clock-cells = <0>;
0010 compatible = "ti,am35xx-gate-clock";
0011 clocks = <&ipss_ick>;
0012 reg = <0x032c>;
0013 ti,bit-shift = <1>;
0014 };
0015
0016 emac_fck: emac_fck@32c {
0017 #clock-cells = <0>;
0018 compatible = "ti,gate-clock";
0019 clocks = <&rmii_ck>;
0020 reg = <0x032c>;
0021 ti,bit-shift = <9>;
0022 };
0023
0024 vpfe_ick: vpfe_ick@32c {
0025 #clock-cells = <0>;
0026 compatible = "ti,am35xx-gate-clock";
0027 clocks = <&ipss_ick>;
0028 reg = <0x032c>;
0029 ti,bit-shift = <2>;
0030 };
0031
0032 vpfe_fck: vpfe_fck@32c {
0033 #clock-cells = <0>;
0034 compatible = "ti,gate-clock";
0035 clocks = <&pclk_ck>;
0036 reg = <0x032c>;
0037 ti,bit-shift = <10>;
0038 };
0039
0040 hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c {
0041 #clock-cells = <0>;
0042 compatible = "ti,am35xx-gate-clock";
0043 clocks = <&ipss_ick>;
0044 reg = <0x032c>;
0045 ti,bit-shift = <0>;
0046 };
0047
0048 hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c {
0049 #clock-cells = <0>;
0050 compatible = "ti,gate-clock";
0051 clocks = <&sys_ck>;
0052 reg = <0x032c>;
0053 ti,bit-shift = <8>;
0054 };
0055
0056 hecc_ck: hecc_ck@32c {
0057 #clock-cells = <0>;
0058 compatible = "ti,am35xx-gate-clock";
0059 clocks = <&sys_ck>;
0060 reg = <0x032c>;
0061 ti,bit-shift = <3>;
0062 };
0063 };
0064 &cm_clocks {
0065 clock@a10 {
0066 compatible = "ti,clksel";
0067 reg = <0xa10>;
0068 #clock-cells = <2>;
0069 #address-cells = <0>;
0070
0071 ipss_ick: clock-ipss-ick {
0072 #clock-cells = <0>;
0073 compatible = "ti,am35xx-interface-clock";
0074 clock-output-names = "ipss_ick";
0075 clocks = <&core_l3_ick>;
0076 ti,bit-shift = <4>;
0077 };
0078
0079 uart4_ick_am35xx: clock-uart4-ick-am35xx {
0080 #clock-cells = <0>;
0081 compatible = "ti,omap3-interface-clock";
0082 clock-output-names = "uart4_ick_am35xx";
0083 clocks = <&core_l4_ick>;
0084 ti,bit-shift = <23>;
0085 };
0086 };
0087
0088 rmii_ck: rmii_ck {
0089 #clock-cells = <0>;
0090 compatible = "fixed-clock";
0091 clock-frequency = <50000000>;
0092 };
0093
0094 pclk_ck: pclk_ck {
0095 #clock-cells = <0>;
0096 compatible = "fixed-clock";
0097 clock-frequency = <27000000>;
0098 };
0099
0100 clock@a00 {
0101 compatible = "ti,clksel";
0102 reg = <0xa00>;
0103 #clock-cells = <2>;
0104 #address-cells = <0>;
0105
0106 uart4_fck_am35xx: clock-uart4-fck-am35xx {
0107 #clock-cells = <0>;
0108 compatible = "ti,wait-gate-clock";
0109 clock-output-names = "uart4_fck_am35xx";
0110 clocks = <&core_48m_fck>;
0111 ti,bit-shift = <23>;
0112 };
0113 };
0114 };
0115
0116 &cm_clockdomains {
0117 core_l3_clkdm: core_l3_clkdm {
0118 compatible = "ti,clockdomain";
0119 clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
0120 <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
0121 <&hecc_ck>;
0122 };
0123
0124 core_l4_clkdm: core_l4_clkdm {
0125 compatible = "ti,clockdomain";
0126 clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
0127 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
0128 <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
0129 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
0130 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
0131 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
0132 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
0133 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
0134 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
0135 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
0136 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
0137 <&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
0138 };
0139 };
