0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for am3517 SoC
0004 *
0005 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 #include "omap3.dtsi"
0009
0010 /* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */
0011 /delete-node/ &aes1_target;
0012 /delete-node/ &aes2_target;
0013
0014 / {
0015 aliases {
0016 serial3 = &uart4;
0017 can = &hecc;
0018 };
0019
0020 cpus {
0021 cpu: cpu@0 {
0022 /* Based on OMAP3630 variants OPP50 and OPP100 */
0023 operating-points-v2 = <&cpu0_opp_table>;
0024
0025 clock-latency = <300000>; /* From legacy driver */
0026 };
0027 };
0028
0029 cpu0_opp_table: opp-table {
0030 compatible = "operating-points-v2-ti-cpu";
0031 syscon = <&scm_conf>;
0032 /*
0033 * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx
0034 * appear to operate at 300MHz as well. Since AM3517 only
0035 * lists one operating voltage, it will remain fixed at 1.2V
0036 */
0037 opp50-300000000 {
0038 opp-hz = /bits/ 64 <300000000>;
0039 opp-microvolt = <1200000>;
0040 opp-supported-hw = <0xffffffff 0xffffffff>;
0041 opp-suspend;
0042 };
0043
0044 opp100-600000000 {
0045 opp-hz = /bits/ 64 <600000000>;
0046 opp-microvolt = <1200000>;
0047 opp-supported-hw = <0xffffffff 0xffffffff>;
0048 };
0049 };
0050
0051 ocp@68000000 {
0052 am35x_otg_hs: am35x_otg_hs@5c040000 {
0053 compatible = "ti,omap3-musb";
0054 ti,hwmods = "am35x_otg_hs";
0055 status = "disabled";
0056 reg = <0x5c040000 0x1000>;
0057 interrupts = <71>;
0058 interrupt-names = "mc";
0059 };
0060
0061 davinci_emac: ethernet@5c000000 {
0062 compatible = "ti,am3517-emac";
0063 ti,hwmods = "davinci_emac";
0064 status = "disabled";
0065 reg = <0x5c000000 0x30000>;
0066 interrupts = <67 68 69 70>;
0067 syscon = <&scm_conf>;
0068 ti,davinci-ctrl-reg-offset = <0x10000>;
0069 ti,davinci-ctrl-mod-reg-offset = <0>;
0070 ti,davinci-ctrl-ram-offset = <0x20000>;
0071 ti,davinci-ctrl-ram-size = <0x2000>;
0072 ti,davinci-rmii-en = /bits/ 8 <1>;
0073 local-mac-address = [ 00 00 00 00 00 00 ];
0074 clocks = <&emac_ick>;
0075 clock-names = "ick";
0076 };
0077
0078 davinci_mdio: mdio@5c030000 {
0079 compatible = "ti,davinci_mdio";
0080 ti,hwmods = "davinci_mdio";
0081 status = "disabled";
0082 reg = <0x5c030000 0x1000>;
0083 bus_freq = <1000000>;
0084 #address-cells = <1>;
0085 #size-cells = <0>;
0086 clocks = <&emac_fck>;
0087 clock-names = "fck";
0088 };
0089
0090 uart4: serial@4809e000 {
0091 compatible = "ti,omap3-uart";
0092 ti,hwmods = "uart4";
0093 status = "disabled";
0094 reg = <0x4809e000 0x400>;
0095 interrupts = <84>;
0096 dmas = <&sdma 55 &sdma 54>;
0097 dma-names = "tx", "rx";
0098 clock-frequency = <48000000>;
0099 };
0100
0101 omap3_pmx_core2: pinmux@480025d8 {
0102 compatible = "ti,omap3-padconf", "pinctrl-single";
0103 reg = <0x480025d8 0x24>;
0104 #address-cells = <1>;
0105 #size-cells = <0>;
0106 #pinctrl-cells = <1>;
0107 #interrupt-cells = <1>;
0108 interrupt-controller;
0109 pinctrl-single,register-width = <16>;
0110 pinctrl-single,function-mask = <0xff1f>;
0111 };
0112
0113 hecc: can@5c050000 {
0114 compatible = "ti,am3517-hecc";
0115 status = "disabled";
0116 reg = <0x5c050000 0x80>,
0117 <0x5c053000 0x180>,
0118 <0x5c052000 0x200>;
0119 reg-names = "hecc", "hecc-ram", "mbx";
0120 interrupts = <24>;
0121 clocks = <&hecc_ck>;
0122 };
0123
0124 /*
0125 * On am3517 the OCP registers do not seem to be accessible
0126 * similar to the omap34xx. Maybe SGX is permanently set to
0127 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
0128 * write-only at 0x50000e10. We detect SGX based on the SGX
0129 * revision register instead of the unreadable OCP revision
0130 * register.
0131 */
0132 sgx_module: target-module@50000000 {
0133 compatible = "ti,sysc-omap2", "ti,sysc";
0134 reg = <0x50000014 0x4>;
0135 reg-names = "rev";
0136 clocks = <&sgx_fck>, <&sgx_ick>;
0137 clock-names = "fck", "ick";
0138 #address-cells = <1>;
0139 #size-cells = <1>;
0140 ranges = <0 0x50000000 0x4000>;
0141
0142 /*
0143 * Closed source PowerVR driver, no child device
0144 * binding or driver in mainline
0145 */
0146 };
0147 };
0148 };
0149
0150 /* Not currently working, probably needs at least different clocks */
0151 &rng_target {
0152 status = "disabled";
0153 /delete-property/ clocks;
0154 };
0155
0156 /* Table Table 5-79 of the TRM shows 480ab000 is reserved */
0157 &usb_otg_hs {
0158 status = "disabled";
0159 };
0160
0161 &iva {
0162 status = "disabled";
0163 };
0164
0165 &mailbox {
0166 status = "disabled";
0167 };
0168
0169 &mmu_isp {
0170 status = "disabled";
0171 };
0172
0173 #include "am35xx-clocks.dtsi"
0174 #include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
0175
0176 /* Preferred always-on timer for clocksource */
0177 &timer1_target {
0178 ti,no-reset-on-init;
0179 ti,no-idle;
0180 timer@0 {
0181 assigned-clocks = <&gpt1_fck>;
0182 assigned-clock-parents = <&sys_ck>;
0183 };
0184 };
0185
0186 /* Preferred timer for clockevent */
0187 &timer2_target {
0188 ti,no-reset-on-init;
0189 ti,no-idle;
0190 timer@0 {
0191 assigned-clocks = <&gpt2_fck>;
0192 assigned-clock-parents = <&sys_ck>;
0193 };
0194 };
