0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for AM33XX SoC
0004 *
0005 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 #include <dt-bindings/bus/ti-sysc.h>
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/pinctrl/am33xx.h>
0011 #include <dt-bindings/clock/am3.h>
0012
0013 / {
0014 compatible = "ti,am33xx";
0015 interrupt-parent = <&intc>;
0016 #address-cells = <1>;
0017 #size-cells = <1>;
0018 chosen { };
0019
0020 aliases {
0021 i2c0 = &i2c0;
0022 i2c1 = &i2c1;
0023 i2c2 = &i2c2;
0024 serial0 = &uart0;
0025 serial1 = &uart1;
0026 serial2 = &uart2;
0027 serial3 = &uart3;
0028 serial4 = &uart4;
0029 serial5 = &uart5;
0030 d-can0 = &dcan0;
0031 d-can1 = &dcan1;
0032 usb0 = &usb0;
0033 usb1 = &usb1;
0034 phy0 = &usb0_phy;
0035 phy1 = &usb1_phy;
0036 ethernet0 = &cpsw_port1;
0037 ethernet1 = &cpsw_port2;
0038 spi0 = &spi0;
0039 spi1 = &spi1;
0040 mmc0 = &mmc1;
0041 mmc1 = &mmc2;
0042 mmc2 = &mmc3;
0043 };
0044
0045 cpus {
0046 #address-cells = <1>;
0047 #size-cells = <0>;
0048 cpu@0 {
0049 compatible = "arm,cortex-a8";
0050 enable-method = "ti,am3352";
0051 device_type = "cpu";
0052 reg = <0>;
0053
0054 operating-points-v2 = <&cpu0_opp_table>;
0055
0056 clocks = <&dpll_mpu_ck>;
0057 clock-names = "cpu";
0058
0059 clock-latency = <300000>; /* From omap-cpufreq driver */
0060 cpu-idle-states = <&mpu_gate>;
0061 };
0062
0063 idle-states {
0064 mpu_gate: mpu_gate {
0065 compatible = "arm,idle-state";
0066 entry-latency-us = <40>;
0067 exit-latency-us = <90>;
0068 min-residency-us = <300>;
0069 ti,idle-wkup-m3;
0070 };
0071 };
0072 };
0073
0074 cpu0_opp_table: opp-table {
0075 compatible = "operating-points-v2-ti-cpu";
0076 syscon = <&scm_conf>;
0077
0078 /*
0079 * The three following nodes are marked with opp-suspend
0080 * because the can not be enabled simultaneously on a
0081 * single SoC.
0082 */
0083 opp50-300000000 {
0084 opp-hz = /bits/ 64 <300000000>;
0085 opp-microvolt = <950000 931000 969000>;
0086 opp-supported-hw = <0x06 0x0010>;
0087 opp-suspend;
0088 };
0089
0090 opp100-275000000 {
0091 opp-hz = /bits/ 64 <275000000>;
0092 opp-microvolt = <1100000 1078000 1122000>;
0093 opp-supported-hw = <0x01 0x00FF>;
0094 opp-suspend;
0095 };
0096
0097 opp100-300000000 {
0098 opp-hz = /bits/ 64 <300000000>;
0099 opp-microvolt = <1100000 1078000 1122000>;
0100 opp-supported-hw = <0x06 0x0020>;
0101 opp-suspend;
0102 };
0103
0104 opp100-500000000 {
0105 opp-hz = /bits/ 64 <500000000>;
0106 opp-microvolt = <1100000 1078000 1122000>;
0107 opp-supported-hw = <0x01 0xFFFF>;
0108 };
0109
0110 opp100-600000000 {
0111 opp-hz = /bits/ 64 <600000000>;
0112 opp-microvolt = <1100000 1078000 1122000>;
0113 opp-supported-hw = <0x06 0x0040>;
0114 };
0115
0116 opp120-600000000 {
0117 opp-hz = /bits/ 64 <600000000>;
0118 opp-microvolt = <1200000 1176000 1224000>;
0119 opp-supported-hw = <0x01 0xFFFF>;
0120 };
0121
0122 opp120-720000000 {
0123 opp-hz = /bits/ 64 <720000000>;
0124 opp-microvolt = <1200000 1176000 1224000>;
0125 opp-supported-hw = <0x06 0x0080>;
0126 };
0127
0128 oppturbo-720000000 {
0129 opp-hz = /bits/ 64 <720000000>;
0130 opp-microvolt = <1260000 1234800 1285200>;
0131 opp-supported-hw = <0x01 0xFFFF>;
0132 };
0133
0134 oppturbo-800000000 {
0135 opp-hz = /bits/ 64 <800000000>;
0136 opp-microvolt = <1260000 1234800 1285200>;
0137 opp-supported-hw = <0x06 0x0100>;
0138 };
0139
0140 oppnitro-1000000000 {
0141 opp-hz = /bits/ 64 <1000000000>;
0142 opp-microvolt = <1325000 1298500 1351500>;
0143 opp-supported-hw = <0x04 0x0200>;
0144 };
0145 };
0146
0147 target-module@4b000000 {
0148 compatible = "ti,sysc-omap4-simple", "ti,sysc";
0149 clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>;
0150 clock-names = "fck";
0151 ti,no-idle;
0152 #address-cells = <1>;
0153 #size-cells = <1>;
0154 ranges = <0x0 0x4b000000 0x1000000>;
0155
0156 target-module@140000 {
0157 compatible = "ti,sysc-omap4-simple", "ti,sysc";
0158 clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
0159 clock-names = "fck";
0160 #address-cells = <1>;
0161 #size-cells = <1>;
0162 ranges = <0x0 0x140000 0xec0000>;
0163
0164 pmu@0 {
0165 compatible = "arm,cortex-a8-pmu";
0166 interrupts = <3>;
0167 };
0168 };
0169 };
0170
0171 /*
0172 * The soc node represents the soc top level view. It is used for IPs
0173 * that are not memory mapped in the MPU view or for the MPU itself.
0174 */
0175 soc {
0176 compatible = "ti,omap-infra";
0177 };
0178
0179 /*
0180 * XXX: Use a flat representation of the AM33XX interconnect.
0181 * The real AM33XX interconnect network is quite complex. Since
0182 * it will not bring real advantage to represent that in DT
0183 * for the moment, just use a fake OCP bus entry to represent
0184 * the whole bus hierarchy.
0185 */
0186 ocp: ocp {
0187 compatible = "simple-pm-bus";
0188 power-domains = <&prm_per>;
0189 clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>;
0190 clock-names = "fck";
0191 #address-cells = <1>;
0192 #size-cells = <1>;
0193 ranges;
0194
0195 l4_wkup: interconnect@44c00000 {
0196 };
0197 l4_per: interconnect@48000000 {
0198 };
0199 l4_fw: interconnect@47c00000 {
0200 };
0201 l4_fast: interconnect@4a000000 {
0202 };
0203 l4_mpuss: interconnect@4b140000 {
0204 };
0205
0206 intc: interrupt-controller@48200000 {
0207 compatible = "ti,am33xx-intc";
0208 interrupt-controller;
0209 #interrupt-cells = <1>;
0210 reg = <0x48200000 0x1000>;
0211 };
0212
0213 target-module@49000000 {
0214 compatible = "ti,sysc-omap4", "ti,sysc";
0215 reg = <0x49000000 0x4>;
0216 reg-names = "rev";
0217 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
0218 clock-names = "fck";
0219 #address-cells = <1>;
0220 #size-cells = <1>;
0221 ranges = <0x0 0x49000000 0x10000>;
0222
0223 edma: dma@0 {
0224 compatible = "ti,edma3-tpcc";
0225 reg = <0 0x10000>;
0226 reg-names = "edma3_cc";
0227 interrupts = <12 13 14>;
0228 interrupt-names = "edma3_ccint", "edma3_mperr",
0229 "edma3_ccerrint";
0230 dma-requests = <64>;
0231 #dma-cells = <2>;
0232
0233 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
0234 <&edma_tptc2 0>;
0235
0236 ti,edma-memcpy-channels = <20 21>;
0237 };
0238 };
0239
0240 target-module@49800000 {
0241 compatible = "ti,sysc-omap4", "ti,sysc";
0242 reg = <0x49800000 0x4>,
0243 <0x49800010 0x4>;
0244 reg-names = "rev", "sysc";
0245 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
0246 ti,sysc-midle = <SYSC_IDLE_FORCE>;
0247 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0248 <SYSC_IDLE_SMART>;
0249 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
0250 clock-names = "fck";
0251 #address-cells = <1>;
0252 #size-cells = <1>;
0253 ranges = <0x0 0x49800000 0x100000>;
0254
0255 edma_tptc0: dma@0 {
0256 compatible = "ti,edma3-tptc";
0257 reg = <0 0x100000>;
0258 interrupts = <112>;
0259 interrupt-names = "edma3_tcerrint";
0260 };
0261 };
0262
0263 target-module@49900000 {
0264 compatible = "ti,sysc-omap4", "ti,sysc";
0265 reg = <0x49900000 0x4>,
0266 <0x49900010 0x4>;
0267 reg-names = "rev", "sysc";
0268 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
0269 ti,sysc-midle = <SYSC_IDLE_FORCE>;
0270 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0271 <SYSC_IDLE_SMART>;
0272 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
0273 clock-names = "fck";
0274 #address-cells = <1>;
0275 #size-cells = <1>;
0276 ranges = <0x0 0x49900000 0x100000>;
0277
0278 edma_tptc1: dma@0 {
0279 compatible = "ti,edma3-tptc";
0280 reg = <0 0x100000>;
0281 interrupts = <113>;
0282 interrupt-names = "edma3_tcerrint";
0283 };
0284 };
0285
0286 target-module@49a00000 {
0287 compatible = "ti,sysc-omap4", "ti,sysc";
0288 reg = <0x49a00000 0x4>,
0289 <0x49a00010 0x4>;
0290 reg-names = "rev", "sysc";
0291 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
0292 ti,sysc-midle = <SYSC_IDLE_FORCE>;
0293 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0294 <SYSC_IDLE_SMART>;
0295 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
0296 clock-names = "fck";
0297 #address-cells = <1>;
0298 #size-cells = <1>;
0299 ranges = <0x0 0x49a00000 0x100000>;
0300
0301 edma_tptc2: dma@0 {
0302 compatible = "ti,edma3-tptc";
0303 reg = <0 0x100000>;
0304 interrupts = <114>;
0305 interrupt-names = "edma3_tcerrint";
0306 };
0307 };
0308
0309 target-module@47810000 {
0310 compatible = "ti,sysc-omap2", "ti,sysc";
0311 reg = <0x478102fc 0x4>,
0312 <0x47810110 0x4>,
0313 <0x47810114 0x4>;
0314 reg-names = "rev", "sysc", "syss";
0315 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0316 SYSC_OMAP2_ENAWAKEUP |
0317 SYSC_OMAP2_SOFTRESET |
0318 SYSC_OMAP2_AUTOIDLE)>;
0319 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0320 <SYSC_IDLE_NO>,
0321 <SYSC_IDLE_SMART>;
0322 ti,syss-mask = <1>;
0323 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
0324 clock-names = "fck";
0325 #address-cells = <1>;
0326 #size-cells = <1>;
0327 ranges = <0x0 0x47810000 0x1000>;
0328
0329 mmc3: mmc@0 {
0330 compatible = "ti,am335-sdhci";
0331 ti,needs-special-reset;
0332 interrupts = <29>;
0333 reg = <0x0 0x1000>;
0334 status = "disabled";
0335 };
0336 };
0337
0338 usb: target-module@47400000 {
0339 compatible = "ti,sysc-omap4", "ti,sysc";
0340 reg = <0x47400000 0x4>,
0341 <0x47400010 0x4>;
0342 reg-names = "rev", "sysc";
0343 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
0344 SYSC_OMAP4_SOFTRESET)>;
0345 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0346 <SYSC_IDLE_NO>,
0347 <SYSC_IDLE_SMART>;
0348 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0349 <SYSC_IDLE_NO>,
0350 <SYSC_IDLE_SMART>,
0351 <SYSC_IDLE_SMART_WKUP>;
0352 clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
0353 clock-names = "fck";
0354 #address-cells = <1>;
0355 #size-cells = <1>;
0356 ranges = <0x0 0x47400000 0x8000>;
0357
0358 usb0_phy: usb-phy@1300 {
0359 compatible = "ti,am335x-usb-phy";
0360 reg = <0x1300 0x100>;
0361 reg-names = "phy";
0362 ti,ctrl_mod = <&usb_ctrl_mod>;
0363 #phy-cells = <0>;
0364 };
0365
0366 usb0: usb@1400 {
0367 compatible = "ti,musb-am33xx";
0368 reg = <0x1400 0x400>,
0369 <0x1000 0x200>;
0370 reg-names = "mc", "control";
0371
0372 interrupts = <18>;
0373 interrupt-names = "mc";
0374 dr_mode = "otg";
0375 mentor,multipoint = <1>;
0376 mentor,num-eps = <16>;
0377 mentor,ram-bits = <12>;
0378 mentor,power = <500>;
0379 phys = <&usb0_phy>;
0380
0381 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
0382 &cppi41dma 2 0 &cppi41dma 3 0
0383 &cppi41dma 4 0 &cppi41dma 5 0
0384 &cppi41dma 6 0 &cppi41dma 7 0
0385 &cppi41dma 8 0 &cppi41dma 9 0
0386 &cppi41dma 10 0 &cppi41dma 11 0
0387 &cppi41dma 12 0 &cppi41dma 13 0
0388 &cppi41dma 14 0 &cppi41dma 0 1
0389 &cppi41dma 1 1 &cppi41dma 2 1
0390 &cppi41dma 3 1 &cppi41dma 4 1
0391 &cppi41dma 5 1 &cppi41dma 6 1
0392 &cppi41dma 7 1 &cppi41dma 8 1
0393 &cppi41dma 9 1 &cppi41dma 10 1
0394 &cppi41dma 11 1 &cppi41dma 12 1
0395 &cppi41dma 13 1 &cppi41dma 14 1>;
0396 dma-names =
0397 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
0398 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
0399 "rx14", "rx15",
0400 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
0401 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
0402 "tx14", "tx15";
0403 };
0404
0405 usb1_phy: usb-phy@1b00 {
0406 compatible = "ti,am335x-usb-phy";
0407 reg = <0x1b00 0x100>;
0408 reg-names = "phy";
0409 ti,ctrl_mod = <&usb_ctrl_mod>;
0410 #phy-cells = <0>;
0411 };
0412
0413 usb1: usb@1800 {
0414 compatible = "ti,musb-am33xx";
0415 reg = <0x1c00 0x400>,
0416 <0x1800 0x200>;
0417 reg-names = "mc", "control";
0418 interrupts = <19>;
0419 interrupt-names = "mc";
0420 dr_mode = "otg";
0421 mentor,multipoint = <1>;
0422 mentor,num-eps = <16>;
0423 mentor,ram-bits = <12>;
0424 mentor,power = <500>;
0425 phys = <&usb1_phy>;
0426
0427 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
0428 &cppi41dma 17 0 &cppi41dma 18 0
0429 &cppi41dma 19 0 &cppi41dma 20 0
0430 &cppi41dma 21 0 &cppi41dma 22 0
0431 &cppi41dma 23 0 &cppi41dma 24 0
0432 &cppi41dma 25 0 &cppi41dma 26 0
0433 &cppi41dma 27 0 &cppi41dma 28 0
0434 &cppi41dma 29 0 &cppi41dma 15 1
0435 &cppi41dma 16 1 &cppi41dma 17 1
0436 &cppi41dma 18 1 &cppi41dma 19 1
0437 &cppi41dma 20 1 &cppi41dma 21 1
0438 &cppi41dma 22 1 &cppi41dma 23 1
0439 &cppi41dma 24 1 &cppi41dma 25 1
0440 &cppi41dma 26 1 &cppi41dma 27 1
0441 &cppi41dma 28 1 &cppi41dma 29 1>;
0442 dma-names =
0443 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
0444 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
0445 "rx14", "rx15",
0446 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
0447 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
0448 "tx14", "tx15";
0449 };
0450
0451 cppi41dma: dma-controller@2000 {
0452 compatible = "ti,am3359-cppi41";
0453 reg = <0x0000 0x1000>,
0454 <0x2000 0x1000>,
0455 <0x3000 0x1000>,
0456 <0x4000 0x4000>;
0457 reg-names = "glue", "controller", "scheduler", "queuemgr";
0458 interrupts = <17>;
0459 interrupt-names = "glue";
0460 #dma-cells = <2>;
0461 /* For backwards compatibility: */
0462 #dma-channels = <30>;
0463 dma-channels = <30>;
0464 #dma-requests = <256>;
0465 dma-requests = <256>;
0466 };
0467 };
0468
0469 target-module@40300000 {
0470 compatible = "ti,sysc-omap4-simple", "ti,sysc";
0471 clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>;
0472 clock-names = "fck";
0473 ti,no-idle;
0474 #address-cells = <1>;
0475 #size-cells = <1>;
0476 ranges = <0 0x40300000 0x10000>;
0477
0478 ocmcram: sram@0 {
0479 compatible = "mmio-sram";
0480 reg = <0 0x10000>; /* 64k */
0481 ranges = <0 0 0x10000>;
0482 #address-cells = <1>;
0483 #size-cells = <1>;
0484
0485 pm_sram_code: pm-code-sram@0 {
0486 compatible = "ti,sram";
0487 reg = <0x0 0x1000>;
0488 protect-exec;
0489 };
0490
0491 pm_sram_data: pm-data-sram@1000 {
0492 compatible = "ti,sram";
0493 reg = <0x1000 0x1000>;
0494 pool;
0495 };
0496 };
0497 };
0498
0499 target-module@4c000000 {
0500 compatible = "ti,sysc-omap4-simple", "ti,sysc";
0501 reg = <0x4c000000 0x4>;
0502 reg-names = "rev";
0503 clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>;
0504 clock-names = "fck";
0505 ti,no-idle;
0506 #address-cells = <1>;
0507 #size-cells = <1>;
0508 ranges = <0x0 0x4c000000 0x1000000>;
0509
0510 emif: emif@0 {
0511 compatible = "ti,emif-am3352";
0512 reg = <0 0x1000000>;
0513 interrupts = <101>;
0514 sram = <&pm_sram_code
0515 &pm_sram_data>;
0516 };
0517 };
0518
0519 target-module@50000000 {
0520 compatible = "ti,sysc-omap2", "ti,sysc";
0521 reg = <0x50000000 4>,
0522 <0x50000010 4>,
0523 <0x50000014 4>;
0524 reg-names = "rev", "sysc", "syss";
0525 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0526 <SYSC_IDLE_NO>,
0527 <SYSC_IDLE_SMART>;
0528 ti,syss-mask = <1>;
0529 clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
0530 clock-names = "fck";
0531 #address-cells = <1>;
0532 #size-cells = <1>;
0533 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
0534 <0x00000000 0x00000000 0x40000000>; /* data */
0535
0536 gpmc: gpmc@50000000 {
0537 compatible = "ti,am3352-gpmc";
0538 reg = <0x50000000 0x2000>;
0539 interrupts = <100>;
0540 dmas = <&edma 52 0>;
0541 dma-names = "rxtx";
0542 gpmc,num-cs = <7>;
0543 gpmc,num-waitpins = <2>;
0544 #address-cells = <2>;
0545 #size-cells = <1>;
0546 interrupt-controller;
0547 #interrupt-cells = <2>;
0548 gpio-controller;
0549 #gpio-cells = <2>;
0550 status = "disabled";
0551 };
0552 };
0553
0554 sham_target: target-module@53100000 {
0555 compatible = "ti,sysc-omap3-sham", "ti,sysc";
0556 reg = <0x53100100 0x4>,
0557 <0x53100110 0x4>,
0558 <0x53100114 0x4>;
0559 reg-names = "rev", "sysc", "syss";
0560 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
0561 SYSC_OMAP2_AUTOIDLE)>;
0562 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0563 <SYSC_IDLE_NO>,
0564 <SYSC_IDLE_SMART>;
0565 ti,syss-mask = <1>;
0566 /* Domains (P, C): per_pwrdm, l3_clkdm */
0567 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
0568 clock-names = "fck";
0569 #address-cells = <1>;
0570 #size-cells = <1>;
0571 ranges = <0x0 0x53100000 0x1000>;
0572
0573 sham: sham@0 {
0574 compatible = "ti,omap4-sham";
0575 reg = <0 0x200>;
0576 interrupts = <109>;
0577 dmas = <&edma 36 0>;
0578 dma-names = "rx";
0579 };
0580 };
0581
0582 aes_target: target-module@53500000 {
0583 compatible = "ti,sysc-omap2", "ti,sysc";
0584 reg = <0x53500080 0x4>,
0585 <0x53500084 0x4>,
0586 <0x53500088 0x4>;
0587 reg-names = "rev", "sysc", "syss";
0588 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
0589 SYSC_OMAP2_AUTOIDLE)>;
0590 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0591 <SYSC_IDLE_NO>,
0592 <SYSC_IDLE_SMART>,
0593 <SYSC_IDLE_SMART_WKUP>;
0594 ti,syss-mask = <1>;
0595 /* Domains (P, C): per_pwrdm, l3_clkdm */
0596 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
0597 clock-names = "fck";
0598 #address-cells = <1>;
0599 #size-cells = <1>;
0600 ranges = <0x0 0x53500000 0x1000>;
0601
0602 aes: aes@0 {
0603 compatible = "ti,omap4-aes";
0604 reg = <0 0xa0>;
0605 interrupts = <103>;
0606 dmas = <&edma 6 0>,
0607 <&edma 5 0>;
0608 dma-names = "tx", "rx";
0609 };
0610 };
0611
0612 target-module@56000000 {
0613 compatible = "ti,sysc-omap4", "ti,sysc";
0614 reg = <0x5600fe00 0x4>,
0615 <0x5600fe10 0x4>;
0616 reg-names = "rev", "sysc";
0617 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0618 <SYSC_IDLE_NO>,
0619 <SYSC_IDLE_SMART>;
0620 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0621 <SYSC_IDLE_NO>,
0622 <SYSC_IDLE_SMART>;
0623 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
0624 clock-names = "fck";
0625 power-domains = <&prm_gfx>;
0626 resets = <&prm_gfx 0>;
0627 reset-names = "rstctrl";
0628 #address-cells = <1>;
0629 #size-cells = <1>;
0630 ranges = <0 0x56000000 0x1000000>;
0631
0632 /*
0633 * Closed source PowerVR driver, no child device
0634 * binding or driver in mainline
0635 */
0636 };
0637 };
0638 };
0639
0640 #include "am33xx-l4.dtsi"
0641 #include "am33xx-clocks.dtsi"
0642
0643 &prcm {
0644 prm_per: prm@c00 {
0645 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
0646 reg = <0xc00 0x100>;
0647 #reset-cells = <1>;
0648 #power-domain-cells = <0>;
0649 };
0650
0651 prm_wkup: prm@d00 {
0652 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
0653 reg = <0xd00 0x100>;
0654 #reset-cells = <1>;
0655 #power-domain-cells = <0>;
0656 };
0657
0658 prm_mpu: prm@e00 {
0659 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
0660 reg = <0xe00 0x100>;
0661 #power-domain-cells = <0>;
0662 };
0663
0664 prm_device: prm@f00 {
0665 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
0666 reg = <0xf00 0x100>;
0667 #reset-cells = <1>;
0668 };
0669
0670 prm_rtc: prm@1000 {
0671 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
0672 reg = <0x1000 0x100>;
0673 #power-domain-cells = <0>;
0674 };
0675
0676 prm_gfx: prm@1100 {
0677 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
0678 reg = <0x1100 0x100>;
0679 #power-domain-cells = <0>;
0680 #reset-cells = <1>;
0681 };
0682
0683 prm_cefuse: prm@1200 {
0684 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
0685 reg = <0x1200 0x100>;
0686 #power-domain-cells = <0>;
0687 };
0688 };
0689
0690 /* Preferred always-on timer for clocksource */
0691 &timer1_target {
0692 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
0693 <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
0694 clock-names = "fck", "ick";
0695 ti,no-reset-on-init;
0696 ti,no-idle;
0697 timer@0 {
0698 assigned-clocks = <&timer1_fck>;
0699 assigned-clock-parents = <&sys_clkin_ck>;
0700 };
0701 };
0702
0703 /* Preferred timer for clockevent */
0704 &timer2_target {
0705 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
0706 <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
0707 clock-names = "fck", "ick";
0708 ti,no-reset-on-init;
0709 ti,no-idle;
0710 timer@0 {
0711 assigned-clocks = <&timer2_fck>;
0712 assigned-clock-parents = <&sys_clkin_ck>;
0713 };
0714 };
