0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2015 Phytec Messtechnik GmbH
0004 * Author: Teresa Remmet <t.remmet@phytec.de>
0005 */
0006
0007 / {
0008 model = "Phytec AM335x phyBOARD-WEGA";
0009 compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
0010
0011 sound: sound_iface {
0012 compatible = "ti,da830-evm-audio";
0013 };
0014
0015 vcc3v3: fixedregulator1 {
0016 compatible = "regulator-fixed";
0017 regulator-name = "vcc3v3";
0018 regulator-min-microvolt = <3300000>;
0019 regulator-max-microvolt = <3300000>;
0020 regulator-boot-on;
0021 };
0022 };
0023
0024 /* Audio */
0025 &am33xx_pinmux {
0026 mcasp0_pins: pinmux_mcasp0 {
0027 pinctrl-single,pins = <
0028 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0029 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
0030 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
0031 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
0032 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0033 >;
0034 };
0035 };
0036
0037 &i2c0 {
0038 tlv320aic3007: tlv320aic3007@18 {
0039 compatible = "ti,tlv320aic3007";
0040 reg = <0x18>;
0041 AVDD-supply = <&vcc3v3>;
0042 IOVDD-supply = <&vcc3v3>;
0043 DRVDD-supply = <&vcc3v3>;
0044 DVDD-supply = <&vdig1_reg>;
0045 status = "okay";
0046 };
0047 };
0048
0049 &mcasp0 {
0050 pinctrl-names = "default";
0051 pinctrl-0 = <&mcasp0_pins>;
0052 op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
0053 tdm-slots = <2>;
0054 serial-dir = <
0055 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */
0056 >;
0057 tx-num-evt = <16>;
0058 rx-num-evt = <16>;
0059 status = "okay";
0060 };
0061
0062 &sound {
0063 ti,model = "AM335x-Wega";
0064 ti,audio-codec = <&tlv320aic3007>;
0065 ti,mcasp-controller = <&mcasp0>;
0066 ti,audio-routing =
0067 "Line Out", "LLOUT",
0068 "Line Out", "RLOUT",
0069 "LINE1L", "Line In",
0070 "LINE1R", "Line In";
0071 clocks = <&mcasp0_fck>;
0072 clock-names = "mclk";
0073 status = "okay";
0074 };
0075
0076 /* CAN Busses */
0077 &am33xx_pinmux {
0078 dcan1_pins: pinmux_dcan1 {
0079 pinctrl-single,pins = <
0080 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
0081 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
0082 >;
0083 };
0084 };
0085
0086 &dcan1 {
0087 pinctrl-names = "default";
0088 pinctrl-0 = <&dcan1_pins>;
0089 status = "okay";
0090 };
0091
0092 /* Ethernet */
0093 &am33xx_pinmux {
0094 ethernet1_pins: pinmux_ethernet1 {
0095 pinctrl-single,pins = <
0096 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */
0097 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */
0098 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */
0099 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */
0100 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */
0101 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */
0102 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */
0103 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */
0104 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
0105 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
0106 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
0107 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
0108 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */
0109 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */
0110 >;
0111 };
0112 };
0113
0114 &cpsw_port2 {
0115 status = "okay";
0116 phy-handle = <&phy1>;
0117 phy-mode = "mii";
0118 ti,dual-emac-pvid = <2>;
0119 };
0120
0121 &davinci_mdio_sw {
0122 phy1: ethernet-phy@1 {
0123 reg = <1>;
0124 };
0125 };
0126
0127 &mac_sw {
0128 pinctrl-names = "default";
0129 pinctrl-0 = <ðernet0_pins ðernet1_pins>;
0130 };
0131
0132 /* MMC */
0133 &am33xx_pinmux {
0134 mmc1_pins: pinmux_mmc1 {
0135 pinctrl-single,pins = <
0136 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
0137 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
0138 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
0139 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
0140 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
0141 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
0142 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */
0143 >;
0144 };
0145 };
0146
0147 &mmc1 {
0148 vmmc-supply = <&vcc3v3>;
0149 bus-width = <4>;
0150 pinctrl-names = "default";
0151 pinctrl-0 = <&mmc1_pins>;
0152 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
0153 status = "okay";
0154 };
0155
0156 /* Power */
0157 &vdig1_reg {
0158 regulator-boot-on;
0159 regulator-always-on;
0160 };
0161
0162 /* UARTs */
0163 &am33xx_pinmux {
0164 uart0_pins: pinmux_uart0 {
0165 pinctrl-single,pins = <
0166 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
0167 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0168 >;
0169 };
0170
0171 uart1_pins: pinmux_uart1_pins {
0172 pinctrl-single,pins = <
0173 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
0174 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0175 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
0176 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0177 >;
0178 };
0179 };
0180
0181 &uart0 {
0182 pinctrl-names = "default";
0183 pinctrl-0 = <&uart0_pins>;
0184 status = "okay";
0185 };
0186
0187 &uart1 {
0188 pinctrl-names = "default";
0189 pinctrl-0 = <&uart1_pins>;
0190 status = "okay";
0191 };
0192
0193 &usb1 {
0194 dr_mode = "host";
0195 };
