0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2019 Phytec Messtechnik GmbH
0004 * Author: Teresa Remmet <t.remmet@phytec.de>
0005 *
0006 */
0007
0008 / {
0009 model = "Phytec AM335x phyBOARD-REGOR";
0010 compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx";
0011
0012 vcc3v3: fixedregulator@1 {
0013 compatible = "regulator-fixed";
0014 regulator-name = "vcc3v3";
0015 regulator-min-microvolt = <3300000>;
0016 regulator-max-microvolt = <3300000>;
0017 regulator-boot-on;
0018 };
0019
0020 /* User IO */
0021 user_leds: user_leds {
0022 compatible = "gpio-leds";
0023 pinctrl-names = "default";
0024 pinctrl-0 = <&user_leds_pins>;
0025
0026 run_stop-led {
0027 gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
0028 linux,default-trigger = "gpio";
0029 default-state = "off";
0030 };
0031
0032 error-led {
0033 gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
0034 linux,default-trigger = "gpio";
0035 default-state = "off";
0036 };
0037 };
0038 };
0039
0040 /* User Leds */
0041 &am33xx_pinmux {
0042 user_leds_pins: pinmux_user_leds {
0043 pinctrl-single,pins = <
0044 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_22 */
0045 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_fsx.gpio3_15 */
0046 >;
0047 };
0048 };
0049
0050 /* CAN Busses */
0051 &am33xx_pinmux {
0052 dcan1_pins: pinmux_dcan1 {
0053 pinctrl-single,pins = <
0054 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
0055 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
0056 >;
0057 };
0058 };
0059
0060 &dcan1 {
0061 pinctrl-names = "default";
0062 pinctrl-0 = <&dcan1_pins>;
0063 status = "okay";
0064 };
0065
0066 /* Ethernet */
0067 &am33xx_pinmux {
0068 ethernet1_pins: pinmux_ethernet1 {
0069 pinctrl-single,pins = <
0070 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */
0071 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */
0072 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */
0073 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */
0074 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */
0075 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */
0076 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */
0077 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */
0078 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
0079 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
0080 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
0081 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
0082 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */
0083 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */
0084 >;
0085 };
0086 };
0087
0088 &cpsw_port2 {
0089 status = "okay";
0090 phy-handle = <&phy1>;
0091 phy-mode = "mii";
0092 ti,dual-emac-pvid = <2>;
0093 };
0094
0095 &davinci_mdio_sw {
0096 phy1: ethernet-phy@1 {
0097 reg = <1>;
0098 };
0099 };
0100
0101 &mac_sw {
0102 pinctrl-names = "default";
0103 pinctrl-0 = <ðernet0_pins ðernet1_pins>;
0104 };
0105
0106 /* GPIOs */
0107 &am33xx_pinmux {
0108 pinctrl-names = "default";
0109 pinctrl-0 = <&user_gpios_pins>;
0110
0111 user_gpios_pins: pinmux_user_gpios {
0112 pinctrl-single,pins = <
0113 /* DIGIN 1-4 */
0114 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7) /* gpmc_ad11.gpio0_27 */
0115 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */
0116 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7) /* gpmc_ad9.gpio0_23 */
0117 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7) /* gpmc_ad8.gpio0_22 */
0118 /* DIGOUT 1-4 */
0119 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad15.gpio1_15 */
0120 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad14.gpio1_14 */
0121 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad13.gpio1_13 */
0122 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad12.gpio1_12 */
0123 >;
0124 };
0125 };
0126
0127 /* MMC */
0128 &am33xx_pinmux {
0129 mmc1_pins: pinmux_mmc1 {
0130 pinctrl-single,pins = <
0131 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
0132 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
0133 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
0134 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
0135 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
0136 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
0137 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */
0138 >;
0139 };
0140 };
0141
0142 &mmc1 {
0143 vmmc-supply = <&vcc3v3>;
0144 bus-width = <4>;
0145 pinctrl-names = "default";
0146 pinctrl-0 = <&mmc1_pins>;
0147 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
0148 status = "okay";
0149 };
0150
0151 /* RTC */
0152 &i2c_rtc {
0153 status = "okay";
0154 };
0155
0156 /* UARTs */
0157 &am33xx_pinmux {
0158 uart0_pins: pinmux_uart0 {
0159 pinctrl-single,pins = <
0160 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
0161 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0162 >;
0163 };
0164
0165 uart2_pins: pinmux_uart2 {
0166 pinctrl-single,pins = <
0167 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */
0168 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */
0169 >;
0170 };
0171 };
0172
0173 &uart0 {
0174 pinctrl-names = "default";
0175 pinctrl-0 = <&uart0_pins>;
0176 status = "okay";
0177 };
0178
0179 &uart2 {
0180 pinctrl-names = "default";
0181 pinctrl-0 = <&uart2_pins>;
0182 status = "okay";
0183 };
0184
0185 /* RS485 - UART1 */
0186 &am33xx_pinmux {
0187 uart1_rs485_pins: pinmux_uart1_rs485_pins {
0188 pinctrl-single,pins = <
0189 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
0190 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0191 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0)
0192 >;
0193 };
0194 };
0195
0196 &uart1 {
0197 pinctrl-names = "default";
0198 pinctrl-0 = <&uart1_rs485_pins>;
0199 status = "okay";
0200 linux,rs485-enabled-at-boot-time;
0201 };
