0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2015 Phytec Messtechnik GmbH
0004 * Author: Teresa Remmet <t.remmet@phytec.de>
0005 */
0006
0007 #include "am33xx.dtsi"
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009
0010 / {
0011 model = "Phytec AM335x phyCORE";
0012 compatible = "phytec,am335x-phycore-som", "ti,am33xx";
0013
0014 aliases {
0015 rtc0 = &i2c_rtc;
0016 rtc1 = &rtc;
0017 };
0018
0019 cpus {
0020 cpu@0 {
0021 cpu0-supply = <&vdd1_reg>;
0022 };
0023 };
0024
0025 memory@80000000 {
0026 device_type = "memory";
0027 reg = <0x80000000 0x10000000>; /* 256 MB */
0028 };
0029
0030 vcc5v: fixedregulator0 {
0031 compatible = "regulator-fixed";
0032 regulator-name = "vcc5v";
0033 regulator-min-microvolt = <5000000>;
0034 regulator-max-microvolt = <5000000>;
0035 regulator-boot-on;
0036 regulator-always-on;
0037 };
0038 };
0039
0040 /* Crypto Module */
0041 &aes {
0042 status = "okay";
0043 };
0044
0045 &sham {
0046 status = "okay";
0047 };
0048
0049 /* EMMC */
0050 &am33xx_pinmux {
0051 emmc_pins: pinmux_emmc_pins {
0052 pinctrl-single,pins = <
0053 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
0054 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
0055 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
0056 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
0057 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
0058 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
0059 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
0060 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
0061 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
0062 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
0063 >;
0064 };
0065 };
0066
0067 &mmc2 {
0068 pinctrl-names = "default";
0069 pinctrl-0 = <&emmc_pins>;
0070 vmmc-supply = <&vmmc_reg>;
0071 bus-width = <8>;
0072 non-removable;
0073 status = "disabled";
0074 };
0075
0076 /* Ethernet */
0077 &am33xx_pinmux {
0078 ethernet0_pins: pinmux_ethernet0 {
0079 pinctrl-single,pins = <
0080 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
0081 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1)
0082 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1)
0083 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1)
0084 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1)
0085 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)
0086 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)
0087 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
0088 >;
0089 };
0090
0091 mdio_pins: pinmux_mdio {
0092 pinctrl-single,pins = <
0093 /* MDIO */
0094 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
0095 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
0096 >;
0097 };
0098 };
0099
0100 &cpsw_port1 {
0101 phy-handle = <&phy0>;
0102 phy-mode = "rmii";
0103 ti,dual-emac-pvid = <1>;
0104 };
0105
0106 &cpsw_port2 {
0107 status = "disabled";
0108 };
0109
0110 &davinci_mdio_sw {
0111 pinctrl-names = "default";
0112 pinctrl-0 = <&mdio_pins>;
0113
0114 phy0: ethernet-phy@0 {
0115 reg = <0>;
0116 };
0117 };
0118
0119 &mac_sw {
0120 pinctrl-names = "default";
0121 pinctrl-0 = <ðernet0_pins>;
0122 status = "okay";
0123 };
0124
0125 /* I2C Busses */
0126 &am33xx_pinmux {
0127 i2c0_pins: pinmux_i2c0 {
0128 pinctrl-single,pins = <
0129 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
0130 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
0131 >;
0132 };
0133 };
0134
0135 &i2c0 {
0136 pinctrl-names = "default";
0137 pinctrl-0 = <&i2c0_pins>;
0138 clock-frequency = <400000>;
0139 status = "okay";
0140
0141 tps: pmic@2d {
0142 reg = <0x2d>;
0143 };
0144
0145 i2c_tmp102: temp@4b {
0146 compatible = "ti,tmp102";
0147 reg = <0x4b>;
0148 status = "disabled";
0149 };
0150
0151 i2c_eeprom: eeprom@52 {
0152 compatible = "atmel,24c32";
0153 pagesize = <32>;
0154 reg = <0x52>;
0155 status = "disabled";
0156 };
0157
0158 i2c_rtc: rtc@68 {
0159 compatible = "microcrystal,rv4162";
0160 reg = <0x68>;
0161 status = "disabled";
0162 };
0163 };
0164
0165 /* NAND memory */
0166 &am33xx_pinmux {
0167 nandflash_pins: pinmux_nandflash {
0168 pinctrl-single,pins = <
0169 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
0170 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
0171 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
0172 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
0173 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
0174 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
0175 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
0176 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
0177 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
0178 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
0179 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
0180 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
0181 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
0182 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
0183 >;
0184 };
0185 };
0186
0187 &elm {
0188 status = "okay";
0189 };
0190
0191 &gpmc {
0192 status = "disabled";
0193 pinctrl-names = "default";
0194 pinctrl-0 = <&nandflash_pins>;
0195 ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
0196 nandflash: nand@0,0 {
0197 compatible = "ti,omap2-nand";
0198 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
0199 interrupt-parent = <&gpmc>;
0200 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
0201 <1 IRQ_TYPE_NONE>; /* termcount */
0202 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
0203 nand-bus-width = <8>;
0204 ti,nand-ecc-opt = "bch8";
0205 gpmc,device-nand = "true";
0206 gpmc,device-width = <1>;
0207 gpmc,sync-clk-ps = <0>;
0208 gpmc,cs-on-ns = <0>;
0209 gpmc,cs-rd-off-ns = <30>;
0210 gpmc,cs-wr-off-ns = <30>;
0211 gpmc,adv-on-ns = <0>;
0212 gpmc,adv-rd-off-ns = <30>;
0213 gpmc,adv-wr-off-ns = <30>;
0214 gpmc,we-on-ns = <0>;
0215 gpmc,we-off-ns = <20>;
0216 gpmc,oe-on-ns = <10>;
0217 gpmc,oe-off-ns = <30>;
0218 gpmc,access-ns = <30>;
0219 gpmc,rd-cycle-ns = <30>;
0220 gpmc,wr-cycle-ns = <30>;
0221 gpmc,bus-turnaround-ns = <0>;
0222 gpmc,cycle2cycle-delay-ns = <50>;
0223 gpmc,cycle2cycle-diffcsen;
0224 gpmc,clk-activation-ns = <0>;
0225 gpmc,wr-access-ns = <30>;
0226 gpmc,wr-data-mux-bus-ns = <0>;
0227
0228 ti,elm-id = <&elm>;
0229
0230 #address-cells = <1>;
0231 #size-cells = <1>;
0232 };
0233 };
0234
0235 /* Power */
0236 #include "tps65910.dtsi"
0237
0238 &tps {
0239 vcc1-supply = <&vcc5v>;
0240 vcc2-supply = <&vcc5v>;
0241 vcc3-supply = <&vcc5v>;
0242 vcc4-supply = <&vcc5v>;
0243 vcc5-supply = <&vcc5v>;
0244 vcc6-supply = <&vcc5v>;
0245 vcc7-supply = <&vcc5v>;
0246 vccio-supply = <&vcc5v>;
0247
0248 regulators {
0249 vrtc_reg: regulator@0 {
0250 regulator-always-on;
0251 };
0252
0253 vio_reg: regulator@1 {
0254 regulator-always-on;
0255 };
0256
0257 vdd1_reg: regulator@2 {
0258 /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
0259 regulator-name = "vdd_mpu";
0260 regulator-min-microvolt = <912500>;
0261 regulator-max-microvolt = <1378000>;
0262 regulator-boot-on;
0263 regulator-always-on;
0264 };
0265
0266 vdd2_reg: regulator@3 {
0267 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
0268 regulator-name = "vdd_core";
0269 regulator-min-microvolt = <912500>;
0270 regulator-max-microvolt = <1150000>;
0271 regulator-boot-on;
0272 regulator-always-on;
0273 };
0274
0275 vdd3_reg: regulator@4 {
0276 regulator-always-on;
0277 };
0278
0279 vdig1_reg: regulator@5 {
0280 regulator-name = "vdig1_1p8v";
0281 regulator-min-microvolt = <1800000>;
0282 regulator-max-microvolt = <1800000>;
0283 };
0284
0285 vdig2_reg: regulator@6 {
0286 regulator-always-on;
0287 };
0288
0289 vpll_reg: regulator@7 {
0290 regulator-always-on;
0291 };
0292
0293 vdac_reg: regulator@8 {
0294 regulator-always-on;
0295 };
0296
0297 vaux1_reg: regulator@9 {
0298 regulator-always-on;
0299 };
0300
0301 vaux2_reg: regulator@10 {
0302 regulator-always-on;
0303 };
0304
0305 vaux33_reg: regulator@11 {
0306 regulator-always-on;
0307 };
0308
0309 vmmc_reg: regulator@12 {
0310 regulator-min-microvolt = <3300000>;
0311 regulator-max-microvolt = <3300000>;
0312 regulator-always-on;
0313 };
0314 };
0315 };
0316
0317 /* SPI Busses */
0318 &am33xx_pinmux {
0319 spi0_pins: pinmux_spi0 {
0320 pinctrl-single,pins = <
0321 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
0322 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0)
0323 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
0324 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
0325 >;
0326 };
0327 };
0328
0329 &spi0 {
0330 pinctrl-names = "default";
0331 pinctrl-0 = <&spi0_pins>;
0332 status = "okay";
0333
0334 serial_flash: flash@0 {
0335 compatible = "jedec,spi-nor";
0336 spi-max-frequency = <48000000>;
0337 reg = <0x0>;
0338 m25p,fast-read;
0339 status = "disabled";
0340 #address-cells = <1>;
0341 #size-cells = <1>;
0342 };
0343 };
