0001 /*
0002 * pdu001.dts
0003 *
0004 * EETS GmbH PDU001 board device tree file
0005 *
0006 * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
0007 *
0008 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
0009 *
0010 * SPDX-License-Identifier: GPL-2.0+
0011 */
0012
0013 /dts-v1/;
0014
0015 #include "am33xx.dtsi"
0016 #include <dt-bindings/interrupt-controller/irq.h>
0017 #include <dt-bindings/leds/leds-pca9532.h>
0018
0019 / {
0020 model = "EETS,PDU001";
0021 compatible = "ti,am33xx";
0022
0023 chosen {
0024 stdout-path = &uart3;
0025 };
0026
0027 cpus {
0028 cpu@0 {
0029 cpu0-supply = <&vdd1_reg>;
0030 };
0031 };
0032
0033 memory {
0034 device_type = "memory";
0035 reg = <0x80000000 0x10000000>; /* 256 MB */
0036 };
0037
0038 vbat: fixedregulator@0 {
0039 compatible = "regulator-fixed";
0040 regulator-name = "vbat";
0041 regulator-min-microvolt = <3600000>;
0042 regulator-max-microvolt = <3600000>;
0043 regulator-boot-on;
0044 };
0045
0046 lis3_reg: fixedregulator@1 {
0047 compatible = "regulator-fixed";
0048 regulator-name = "lis3_reg";
0049 regulator-boot-on;
0050 };
0051
0052 panel {
0053 compatible = "ti,tilcdc,panel";
0054 status = "okay";
0055 pinctrl-names = "default";
0056 pinctrl-0 = <&lcd_pins_s0>;
0057 panel-info {
0058 ac-bias = <255>;
0059 ac-bias-intrpt = <0>;
0060 dma-burst-sz = <16>;
0061 bpp = <16>;
0062 fdd = <0x80>;
0063 sync-edge = <0>;
0064 sync-ctrl = <1>;
0065 raster-order = <0>;
0066 fifo-th = <0>;
0067 };
0068
0069 display-timings {
0070 240x320p16 {
0071 clock-frequency = <6500000>;
0072 hactive = <240>;
0073 vactive = <320>;
0074 hfront-porch = <6>;
0075 hback-porch = <6>;
0076 hsync-len = <1>;
0077 vback-porch = <6>;
0078 vfront-porch = <6>;
0079 vsync-len = <1>;
0080 hsync-active = <0>;
0081 vsync-active = <0>;
0082 pixelclk-active = <1>;
0083 de-active = <0>;
0084 };
0085 };
0086 };
0087 };
0088
0089 &am33xx_pinmux {
0090 pinctrl-names = "default";
0091 pinctrl-0 = <&clkout2_pin>;
0092
0093 i2c0_pins: pinmux_i2c0_pins {
0094 pinctrl-single,pins = <
0095 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
0096 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
0097 >;
0098 };
0099
0100 i2c1_pins: pinmux_i2c1_pins {
0101 pinctrl-single,pins = <
0102 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */
0103 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */
0104 >;
0105 };
0106
0107 i2c2_pins: pinmux_i2c2_pins {
0108 pinctrl-single,pins = <
0109 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_clk.i2c2_sda */
0110 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */
0111 >;
0112 };
0113
0114 spi1_pins: pinmux_spi1_pins {
0115 pinctrl-single,pins = <
0116 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */
0117 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
0118 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
0119 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
0120 >;
0121 };
0122
0123 uart0_pins: pinmux_uart0_pins {
0124 pinctrl-single,pins = <
0125 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7)
0126 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
0127 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0128 >;
0129 };
0130
0131 uart1_pins: pinmux_uart1_pins {
0132 pinctrl-single,pins = <
0133 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
0134 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0135 >;
0136 };
0137
0138 uart3_pins: pinmux_uart3_pins {
0139 pinctrl-single,pins = <
0140 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) /* spi0_cs1.uart3_rxd */
0141 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
0142 >;
0143 };
0144
0145 clkout2_pin: pinmux_clkout2_pin {
0146 pinctrl-single,pins = <
0147 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */
0148 >;
0149 };
0150
0151 cpsw_default: cpsw_default {
0152 pinctrl-single,pins = <
0153 /* Port 1 (emac0) */
0154 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0)
0155 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0)
0156 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0)
0157 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0)
0158 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0)
0159 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0)
0160 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0)
0161 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0)
0162 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0)
0163 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0)
0164 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0)
0165 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0)
0166 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0)
0167 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0)
0168 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0)
0169
0170 /* Port 2 (emac1) */
0171 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* mii2_txen.gpmc_a0 */
0172 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1) /* mii2_rxdv.gpmc_a1 */
0173 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* mii2_txd3.gpmc_a2 */
0174 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* mii2_txd2.gpmc_a3 */
0175 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* mii2_txd1.gpmc_a4 */
0176 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* mii2_txd0.gpmc_a5 */
0177 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1) /* mii2_txclk.gpmc_a6 */
0178 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1) /* mii2_rxclk.gpmc_a7 */
0179 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1) /* mii2_rxd3.gpmc_a8 */
0180 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1) /* mii2_rxd2.gpmc_a9 */
0181 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1) /* mii2_rxd1.gpmc_a10 */
0182 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1) /* mii2_rxd0.gpmc_a11 */
0183 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1) /* mii2_crs.gpmc_wait0 */
0184 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1) /* mii2_rxer.gpmc_wpn */
0185 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1) /* mii2_col.gpmc_ben1 */
0186 >;
0187 };
0188
0189 davinci_mdio_default: davinci_mdio_default {
0190 pinctrl-single,pins = <
0191 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
0192 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
0193 >;
0194 };
0195
0196 mmc1_pins: pinmux_mmc1_pins {
0197 /* eMMC */
0198 pinctrl-single,pins = <
0199 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
0200 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
0201 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
0202 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
0203 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
0204 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
0205 >;
0206 };
0207
0208 mmc2_pins: pinmux_mmc2_pins {
0209 /* SD cardcage */
0210 pinctrl-single,pins = <
0211 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
0212 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
0213 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
0214 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
0215 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
0216 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
0217 /* card change signal for frontpanel SD cardcage */
0218 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
0219 >;
0220 };
0221
0222 lcd_pins_s0: lcd_pins_s0 {
0223 pinctrl-single,pins = <
0224 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
0225 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
0226 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
0227 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
0228 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
0229 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
0230 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
0231 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
0232 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
0233 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
0234 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
0235 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
0236 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
0237 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
0238 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
0239 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
0240 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
0241 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
0242 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
0243 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
0244 >;
0245 };
0246
0247 dcan0_pins: pinmux_dcan0_pins {
0248 pinctrl-single,pins = <
0249 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_ctsn.d_can0_tx */
0250 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart1_rtsn.d_can0_rx */
0251 >;
0252 };
0253 };
0254
0255 &uart0 {
0256 pinctrl-names = "default";
0257 pinctrl-0 = <&uart0_pins>;
0258
0259 rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
0260 rs485-rts-active-high;
0261 rs485-rts-delay = <0 0>;
0262 linux,rs485-enabled-at-boot-time;
0263
0264 status = "okay";
0265 };
0266
0267 &uart1 {
0268 pinctrl-names = "default";
0269 pinctrl-0 = <&uart1_pins>;
0270
0271 status = "okay";
0272 };
0273
0274 &uart3 {
0275 pinctrl-names = "default";
0276 pinctrl-0 = <&uart3_pins>;
0277
0278 status = "okay";
0279 };
0280
0281 &i2c0 {
0282 pinctrl-names = "default";
0283 pinctrl-0 = <&i2c0_pins>;
0284
0285 status = "okay";
0286 clock-frequency = <400000>;
0287
0288 tps: tps@2d {
0289 reg = <0x2d>;
0290 };
0291
0292 m2_eeprom: m2_eeprom@50 {
0293 compatible = "atmel,24c256";
0294 reg = <0x50>;
0295 status = "okay";
0296 };
0297 };
0298
0299 &i2c1 {
0300 pinctrl-names = "default";
0301 pinctrl-0 = <&i2c1_pins>;
0302
0303 status = "okay";
0304 clock-frequency = <100000>;
0305
0306 board_24aa025e48: board_24aa025e48@50 {
0307 compatible = "atmel,24c02";
0308 reg = <0x50>;
0309 };
0310
0311 backplane_24aa025e48: backplane_24aa025e48@53 {
0312 compatible = "atmel,24c02";
0313 reg = <0x53>;
0314 };
0315
0316 pca9532: pca9532@60 {
0317 compatible = "nxp,pca9532";
0318 reg = <0x60>;
0319 psc0 = <0x97>;
0320 pwm0 = <0x80>;
0321 psc1 = <0x97>;
0322 pwm1 = <0x10>;
0323
0324 run.red@0 {
0325 type = <PCA9532_TYPE_LED>;
0326 };
0327 run.green@1 {
0328 type = <PCA9532_TYPE_LED>;
0329 default-state = "on";
0330 };
0331 s2.red@2 {
0332 type = <PCA9532_TYPE_LED>;
0333 };
0334 s2.green@3 {
0335 type = <PCA9532_TYPE_LED>;
0336 };
0337 s1.yellow@4 {
0338 type = <PCA9532_TYPE_LED>;
0339 };
0340 s1.green@5 {
0341 type = <PCA9532_TYPE_LED>;
0342 };
0343 };
0344
0345 pca9530: pca9530@61 {
0346 compatible = "nxp,pca9530";
0347 reg = <0x61>;
0348
0349 tft-panel@0 {
0350 type = <PCA9532_TYPE_LED>;
0351 linux,default-trigger = "backlight";
0352 default-state = "on";
0353 };
0354 };
0355
0356 mcp79400: rtc@6f {
0357 compatible = "microchip,mcp7940x";
0358 reg = <0x6f>;
0359 };
0360 };
0361
0362 &i2c2 {
0363 pinctrl-names = "default";
0364 pinctrl-0 = <&i2c2_pins>;
0365
0366 status = "okay";
0367 clock-frequency = <100000>;
0368 };
0369
0370 &spi1 {
0371 pinctrl-names = "default";
0372 pinctrl-0 = <&spi1_pins>;
0373 ti,pindir-d0-out-d1-in;
0374 status = "okay";
0375
0376 display-controller@0 {
0377 compatible = "orisetech,otm3225a";
0378 reg = <0>;
0379 spi-max-frequency = <1000000>;
0380 // SPI mode 3
0381 spi-cpol;
0382 spi-cpha;
0383 status = "okay";
0384 };
0385 };
0386
0387 /*
0388 * Disable soc's rtc as we have no VBAT for it. This makes the board
0389 * rtc (Microchip MCP79400) the default rtc device 'rtc0'.
0390 */
0391 &rtc {
0392 status = "disabled";
0393 };
0394
0395 &lcdc {
0396 status = "okay";
0397 };
0398
0399 &elm {
0400 status = "okay";
0401 };
0402
0403 #include "tps65910.dtsi"
0404
0405 &tps {
0406 vcc1-supply = <&vbat>;
0407 vcc2-supply = <&vbat>;
0408 vcc3-supply = <&vbat>;
0409 vcc4-supply = <&vbat>;
0410 vcc5-supply = <&vbat>;
0411 vcc6-supply = <&vbat>;
0412 vcc7-supply = <&vbat>;
0413 vccio-supply = <&vbat>;
0414
0415 regulators {
0416 vrtc_reg: regulator@0 {
0417 regulator-name = "ldo_vrtc";
0418 regulator-always-on;
0419 };
0420
0421 vio_reg: regulator@1 {
0422 regulator-name = "buck_vdd_ddr";
0423 regulator-always-on;
0424 };
0425
0426 vdd1_reg: regulator@2 {
0427 /* VDD_MPU voltage limits */
0428 regulator-name = "buck_vdd_mpu";
0429 regulator-min-microvolt = <912500>;
0430 regulator-max-microvolt = <1312500>;
0431 regulator-boot-on;
0432 regulator-always-on;
0433 };
0434
0435 vdd2_reg: regulator@3 {
0436 /* VDD_CORE voltage limits */
0437 regulator-name = "buck_vdd_core";
0438 regulator-min-microvolt = <912500>;
0439 regulator-max-microvolt = <1150000>;
0440 regulator-boot-on;
0441 regulator-always-on;
0442 };
0443
0444 vdd3_reg: regulator@4 {
0445 regulator-name = "boost_res";
0446 regulator-always-on;
0447 };
0448
0449 vdig1_reg: regulator@5 {
0450 regulator-name = "ldo_vdig1";
0451 regulator-always-on;
0452 };
0453
0454 vdig2_reg: regulator@6 {
0455 regulator-name = "ldo_vdig2";
0456 regulator-always-on;
0457 };
0458
0459 vpll_reg: regulator@7 {
0460 regulator-name = "ldo_vpll";
0461 regulator-always-on;
0462 };
0463
0464 vdac_reg: regulator@8 {
0465 regulator-name = "ldo_vdac";
0466 regulator-always-on;
0467 };
0468
0469 vaux1_reg: regulator@9 {
0470 regulator-name = "ldo_vaux1";
0471 regulator-always-on;
0472 };
0473
0474 vaux2_reg: regulator@10 {
0475 regulator-name = "ldo_vaux2";
0476 regulator-always-on;
0477 };
0478
0479 vaux33_reg: regulator@11 {
0480 regulator-name = "ldo_vaux33";
0481 regulator-always-on;
0482 };
0483
0484 vmmc_reg: regulator@12 {
0485 regulator-name = "ldo_vmmc";
0486 regulator-min-microvolt = <1800000>;
0487 regulator-max-microvolt = <3300000>;
0488 regulator-always-on;
0489 };
0490
0491 vbb_reg: regulator@13 {
0492 regulator-name = "bat_vbb";
0493 };
0494 };
0495 };
0496
0497 &mac_sw {
0498 pinctrl-names = "default";
0499 pinctrl-0 = <&cpsw_default>;
0500 status = "okay";
0501 };
0502
0503 &davinci_mdio_sw {
0504 pinctrl-names = "default";
0505 pinctrl-0 = <&davinci_mdio_default>;
0506
0507 ethphy0: ethernet-phy@0 {
0508 reg = <0>;
0509 };
0510
0511 ethphy1: ethernet-phy@1 {
0512 reg = <1>;
0513 };
0514 };
0515
0516 &cpsw_port1 {
0517 phy-handle = <ðphy0>;
0518 phy-mode = "mii";
0519 ti,dual-emac-pvid = <1>;
0520 };
0521
0522 &cpsw_port2 {
0523 phy-handle = <ðphy1>;
0524 phy-mode = "mii";
0525 ti,dual-emac-pvid = <2>;
0526 };
0527
0528 &tscadc {
0529 status = "okay";
0530 tsc {
0531 ti,wires = <4>;
0532 ti,x-plate-resistance = <200>;
0533 ti,coordinate-readouts = <5>;
0534 ti,wire-config = <0x01 0x10 0x22 0x33>;
0535 ti,charge-delay = <0x400>;
0536 };
0537
0538 adc {
0539 ti,adc-channels = <4 5 6 7>;
0540 };
0541 };
0542
0543 &mmc1 {
0544 status = "okay";
0545 vmmc-supply = <&vmmc_reg>;
0546 bus-width = <4>;
0547 pinctrl-names = "default";
0548 pinctrl-0 = <&mmc1_pins>;
0549 non-removable;
0550 };
0551
0552 &mmc2 {
0553 status = "okay";
0554 vmmc-supply = <&vmmc_reg>;
0555 bus-width = <4>;
0556 pinctrl-names = "default";
0557 pinctrl-0 = <&mmc2_pins>;
0558 cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
0559 };
0560
0561 &sham {
0562 status = "okay";
0563 };
0564
0565 &aes {
0566 status = "okay";
0567 };
0568
0569 &dcan0 {
0570 status = "okay";
0571 pinctrl-names = "default";
0572 pinctrl-0 = <&dcan0_pins>;
0573 };
