0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/
0004 */
0005 /dts-v1/;
0006
0007 #include "am33xx.dtsi"
0008
0009 / {
0010 model = "Newflow AM335x NanoBone";
0011 compatible = "ti,am33xx";
0012
0013 cpus {
0014 cpu@0 {
0015 cpu0-supply = <&dcdc2_reg>;
0016 };
0017 };
0018
0019 memory@80000000 {
0020 device_type = "memory";
0021 reg = <0x80000000 0x10000000>; /* 256 MB */
0022 };
0023
0024 leds {
0025 compatible = "gpio-leds";
0026
0027 led0 {
0028 label = "nanobone:green:usr1";
0029 gpios = <&gpio1 5 0>;
0030 default-state = "off";
0031 };
0032 };
0033 };
0034
0035 &am33xx_pinmux {
0036 pinctrl-names = "default";
0037 pinctrl-0 = <&misc_pins>;
0038
0039 misc_pins: misc_pins {
0040 pinctrl-single,pins = <
0041 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) /* spi0_cs0.gpio0_5 */
0042 >;
0043 };
0044
0045 gpmc_pins: gpmc_pins {
0046 pinctrl-single,pins = <
0047 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
0048 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
0049 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
0050 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
0051 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
0052 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
0053 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
0054 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
0055 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE0)
0056 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE0)
0057 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE0)
0058 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE0)
0059 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE0)
0060 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE0)
0061 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE0)
0062 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE0)
0063
0064 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
0065 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
0066 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE0)
0067 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT, MUX_MODE0)
0068 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE0)
0069
0070 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
0071 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
0072 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
0073 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
0074
0075 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE1) /* lcd_data1.gpmc_a1 */
0076 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE1) /* lcd_data2.gpmc_a2 */
0077 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE1) /* lcd_data3.gpmc_a3 */
0078 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE1) /* lcd_data4.gpmc_a4 */
0079 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE1) /* lcd_data5.gpmc_a5 */
0080 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE1) /* lcd_data6.gpmc_a6 */
0081 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE1) /* lcd_data7.gpmc_a7 */
0082
0083 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_vsync.gpmc_a8 */
0084 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_hsync.gpmc_a9 */
0085 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE1) /* lcd_pclk.gpmc_a10 */
0086 >;
0087 };
0088
0089 i2c0_pins: i2c0_pins {
0090 pinctrl-single,pins = <
0091 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE0)
0092 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE0)
0093 >;
0094 };
0095
0096 uart0_pins: uart0_pins {
0097 pinctrl-single,pins = <
0098 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
0099 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0)
0100 >;
0101 };
0102
0103 uart1_pins: uart1_pins {
0104 pinctrl-single,pins = <
0105 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE7)
0106 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE7)
0107 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
0108 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
0109 >;
0110 };
0111
0112 uart2_pins: uart2_pins {
0113 pinctrl-single,pins = <
0114 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data8.gpio2[14] */
0115 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) /* lcd_data9.gpio2[15] */
0116 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */
0117 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */
0118 >;
0119 };
0120
0121 uart3_pins: uart3_pins {
0122 pinctrl-single,pins = <
0123 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data10.uart3_ctsn */
0124 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE6) /* lcd_data11.uart3_rtsn */
0125 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */
0126 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
0127 >;
0128 };
0129
0130 uart4_pins: uart4_pins {
0131 pinctrl-single,pins = <
0132 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data12.uart4_ctsn */
0133 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE6) /* lcd_data13.uart4_rtsn */
0134 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */
0135 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */
0136 >;
0137 };
0138
0139 uart5_pins: uart5_pins {
0140 pinctrl-single,pins = <
0141 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE4) /* lcd_data14.uart5_rxd */
0142 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT, MUX_MODE3) /* rmiii1_refclk.uart5_txd */
0143 >;
0144 };
0145
0146 mmc1_pins: mmc1_pins {
0147 pinctrl-single,pins = <
0148 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
0149 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
0150 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
0151 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
0152 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk.mmc0_clk */
0153 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
0154 AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */
0155 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */
0156 >;
0157 };
0158 };
0159
0160 &uart0 {
0161 pinctrl-names = "default";
0162 pinctrl-0 = <&uart0_pins>;
0163 status = "okay";
0164 };
0165
0166 &uart1 {
0167 pinctrl-names = "default";
0168 pinctrl-0 = <&uart1_pins>;
0169 status = "okay";
0170 rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
0171 rs485-rts-active-high;
0172 rs485-rx-during-tx;
0173 rs485-rts-delay = <1 1>;
0174 linux,rs485-enabled-at-boot-time;
0175 };
0176
0177 &uart2 {
0178 pinctrl-names = "default";
0179 pinctrl-0 = <&uart2_pins>;
0180 status = "okay";
0181 rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
0182 rs485-rts-active-high;
0183 rs485-rts-delay = <1 1>;
0184 linux,rs485-enabled-at-boot-time;
0185 };
0186
0187 &uart3 {
0188 pinctrl-names = "default";
0189 pinctrl-0 = <&uart3_pins>;
0190 status = "okay";
0191 };
0192
0193 &uart4 {
0194 pinctrl-names = "default";
0195 pinctrl-0 = <&uart4_pins>;
0196 status = "okay";
0197 };
0198
0199 &uart5 {
0200 pinctrl-names = "default";
0201 pinctrl-0 = <&uart5_pins>;
0202 status = "okay";
0203 };
0204
0205 &i2c0 {
0206 status = "okay";
0207 pinctrl-names = "default";
0208 clock-frequency = <400000>;
0209 pinctrl-names = "default";
0210 pinctrl-0 = <&i2c0_pins>;
0211
0212 gpio@20 {
0213 compatible = "microchip,mcp23017";
0214 gpio-controller;
0215 #gpio-cells = <2>;
0216 reg = <0x20>;
0217 };
0218
0219 tps: tps@24 {
0220 reg = <0x24>;
0221 };
0222
0223 eeprom@53 {
0224 compatible = "microchip,24c02", "atmel,24c02";
0225 reg = <0x53>;
0226 pagesize = <8>;
0227 };
0228
0229 rtc@68 {
0230 compatible = "dallas,ds1307";
0231 reg = <0x68>;
0232 };
0233 };
0234
0235 &elm {
0236 status = "okay";
0237 };
0238
0239 &gpmc {
0240 compatible = "ti,am3352-gpmc";
0241 status = "okay";
0242 gpmc,num-waitpins = <2>;
0243 pinctrl-names = "default";
0244 pinctrl-0 = <&gpmc_pins>;
0245
0246 #address-cells = <2>;
0247 #size-cells = <1>;
0248 ranges = <0 0 0x08000000 0x08000000>, /* CS0: NOR 128M */
0249 <1 0 0x1c000000 0x01000000>; /* CS1: FRAM 16M */
0250
0251 nor@0,0 {
0252 reg = <0 0x00000000 0x08000000>;
0253 compatible = "cfi-flash";
0254 linux,mtd-name = "spansion,s29gl010p11t";
0255 bank-width = <2>;
0256
0257 gpmc,mux-add-data = <2>;
0258
0259 gpmc,sync-clk-ps = <0>;
0260 gpmc,cs-on-ns = <0>;
0261 gpmc,cs-rd-off-ns = <160>;
0262 gpmc,cs-wr-off-ns = <160>;
0263 gpmc,adv-on-ns = <10>;
0264 gpmc,adv-rd-off-ns = <30>;
0265 gpmc,adv-wr-off-ns = <30>;
0266 gpmc,oe-on-ns = <40>;
0267 gpmc,oe-off-ns = <160>;
0268 gpmc,we-on-ns = <40>;
0269 gpmc,we-off-ns = <160>;
0270 gpmc,rd-cycle-ns = <160>;
0271 gpmc,wr-cycle-ns = <160>;
0272 gpmc,access-ns = <150>;
0273 gpmc,page-burst-access-ns = <10>;
0274 gpmc,cycle2cycle-samecsen;
0275 gpmc,cycle2cycle-delay-ns = <20>;
0276 gpmc,wr-data-mux-bus-ns = <70>;
0277 gpmc,wr-access-ns = <80>;
0278
0279 #address-cells = <1>;
0280 #size-cells = <1>;
0281
0282 /*
0283 MTD partition table
0284 ===================
0285 +------------+-->0x00000000-> U-Boot start
0286 | |
0287 | |-->0x000BFFFF-> U-Boot end
0288 | |-->0x000C0000-> ENV1 start
0289 | |
0290 | |-->0x000DFFFF-> ENV1 end
0291 | |-->0x000E0000-> ENV2 start
0292 | |
0293 | |-->0x000FFFFF-> ENV2 end
0294 | |-->0x00100000-> Kernel start
0295 | |
0296 | |-->0x004FFFFF-> Kernel end
0297 | |-->0x00500000-> File system start
0298 | |
0299 | |-->0x01FFFFFF-> File system end
0300 | |-->0x02000000-> User data start
0301 | |
0302 | |-->0x03FFFFFF-> User data end
0303 | |-->0x04000000-> Data storage start
0304 | |
0305 +------------+-->0x08000000-> NOR end (Free end)
0306 */
0307 partition@0 {
0308 label = "boot";
0309 reg = <0x00000000 0x000c0000>; /* 768KB */
0310 };
0311
0312 partition@1 {
0313 label = "env1";
0314 reg = <0x000c0000 0x00020000>; /* 128KB */
0315 };
0316
0317 partition@2 {
0318 label = "env2";
0319 reg = <0x000e0000 0x00020000>; /* 128KB */
0320 };
0321
0322 partition@3 {
0323 label = "kernel";
0324 reg = <0x00100000 0x00400000>; /* 4MB */
0325 };
0326
0327 partition@4 {
0328 label = "rootfs";
0329 reg = <0x00500000 0x01b00000>; /* 27MB */
0330 };
0331
0332 partition@5 {
0333 label = "user";
0334 reg = <0x02000000 0x02000000>; /* 32MB */
0335 };
0336
0337 partition@6 {
0338 label = "data";
0339 reg = <0x04000000 0x04000000>; /* 64MB */
0340 };
0341 };
0342
0343 fram@1,0 {
0344 reg = <1 0x00000000 0x01000000>;
0345 bank-width = <2>;
0346
0347 gpmc,mux-add-data = <2>;
0348
0349 gpmc,sync-clk-ps = <0>;
0350 gpmc,cs-on-ns = <0>;
0351 gpmc,cs-rd-off-ns = <160>;
0352 gpmc,cs-wr-off-ns = <160>;
0353 gpmc,adv-on-ns = <10>;
0354 gpmc,adv-rd-off-ns = <20>;
0355 gpmc,adv-wr-off-ns = <20>;
0356 gpmc,oe-on-ns = <30>;
0357 gpmc,oe-off-ns = <150>;
0358 gpmc,we-on-ns = <30>;
0359 gpmc,we-off-ns = <150>;
0360 gpmc,rd-cycle-ns = <160>;
0361 gpmc,wr-cycle-ns = <160>;
0362 gpmc,access-ns = <130>;
0363 gpmc,page-burst-access-ns = <10>;
0364 gpmc,cycle2cycle-samecsen;
0365 gpmc,cycle2cycle-diffcsen;
0366 gpmc,cycle2cycle-delay-ns = <10>;
0367 gpmc,wr-data-mux-bus-ns = <30>;
0368 gpmc,wr-access-ns = <0>;
0369 };
0370 };
0371
0372 &mac_sw {
0373 status = "okay";
0374 };
0375
0376 &davinci_mdio_sw {
0377 status = "okay";
0378
0379 ethphy0: ethernet-phy@0 {
0380 reg = <0>;
0381 };
0382
0383 ethphy1: ethernet-phy@1 {
0384 reg = <1>;
0385 };
0386 };
0387
0388 &cpsw_port1 {
0389 phy-handle = <ðphy0>;
0390 phy-mode = "mii";
0391 ti,dual-emac-pvid = <1>;
0392 };
0393
0394 &cpsw_port2 {
0395 phy-handle = <ðphy1>;
0396 phy-mode = "mii";
0397 ti,dual-emac-pvid = <2>;
0398 };
0399
0400 &mmc1 {
0401 status = "okay";
0402 vmmc-supply = <&ldo4_reg>;
0403 pinctrl-names = "default";
0404 pinctrl-0 = <&mmc1_pins>;
0405 bus-width = <4>;
0406 cd-gpios = <&gpio3 8 0>;
0407 wp-gpios = <&gpio3 18 0>;
0408 };
0409
0410 #include "tps65217.dtsi"
0411
0412 &tps {
0413 regulators {
0414 dcdc1_reg: regulator@0 {
0415 /* +1.5V voltage with ±4% tolerance */
0416 regulator-min-microvolt = <1450000>;
0417 regulator-max-microvolt = <1550000>;
0418 regulator-boot-on;
0419 regulator-always-on;
0420 };
0421
0422 dcdc2_reg: regulator@1 {
0423 /* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */
0424 regulator-name = "vdd_mpu";
0425 regulator-min-microvolt = <915000>;
0426 regulator-max-microvolt = <1140000>;
0427 regulator-boot-on;
0428 regulator-always-on;
0429 };
0430
0431 dcdc3_reg: regulator@2 {
0432 /* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */
0433 regulator-name = "vdd_core";
0434 regulator-min-microvolt = <915000>;
0435 regulator-max-microvolt = <1140000>;
0436 regulator-boot-on;
0437 regulator-always-on;
0438 };
0439
0440 ldo1_reg: regulator@3 {
0441 /* +1.8V voltage with ±4% tolerance */
0442 regulator-min-microvolt = <1750000>;
0443 regulator-max-microvolt = <1870000>;
0444 regulator-boot-on;
0445 regulator-always-on;
0446 };
0447
0448 ldo2_reg: regulator@4 {
0449 /* +3.3V voltage with ±4% tolerance */
0450 regulator-min-microvolt = <3175000>;
0451 regulator-max-microvolt = <3430000>;
0452 regulator-boot-on;
0453 regulator-always-on;
0454 };
0455
0456 ldo3_reg: regulator@5 {
0457 /* +1.8V voltage with ±4% tolerance */
0458 regulator-min-microvolt = <1750000>;
0459 regulator-max-microvolt = <1870000>;
0460 regulator-boot-on;
0461 regulator-always-on;
0462 };
0463
0464 ldo4_reg: regulator@6 {
0465 /* +3.3V voltage with ±4% tolerance */
0466 regulator-min-microvolt = <3175000>;
0467 regulator-max-microvolt = <3430000>;
0468 regulator-boot-on;
0469 regulator-always-on;
0470 };
0471 };
0472 };
