0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
0003
0004 /* Based on code by myc_c335x.dts, MYiRtech.com */
0005 /* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */
0006
0007 /dts-v1/;
0008
0009 #include "am33xx.dtsi"
0010
0011 #include <dt-bindings/interrupt-controller/irq.h>
0012 #include <dt-bindings/leds/common.h>
0013
0014 / {
0015 model = "MYIR MYC-AM335X";
0016 compatible = "myir,myc-am335x", "ti,am33xx";
0017
0018 cpus {
0019 cpu@0 {
0020 cpu0-supply = <&vdd_core>;
0021 voltage-tolerance = <2>;
0022 };
0023 };
0024
0025 memory@80000000 {
0026 device_type = "memory";
0027 reg = <0x80000000 0x10000000>;
0028 };
0029
0030 clk32k: clk32k {
0031 compatible = "fixed-clock";
0032 clock-frequency = <32768>;
0033
0034 #clock-cells = <0>;
0035 };
0036
0037 vdd_mod: vdd_mod_reg {
0038 compatible = "regulator-fixed";
0039 regulator-name = "vdd-mod";
0040 regulator-always-on;
0041 regulator-boot-on;
0042 };
0043
0044 vdd_core: vdd_core_reg {
0045 compatible = "regulator-fixed";
0046 regulator-name = "vdd-core";
0047 regulator-always-on;
0048 regulator-boot-on;
0049 vin-supply = <&vdd_mod>;
0050 };
0051
0052 leds: leds {
0053 compatible = "gpio-leds";
0054 pinctrl-names = "default";
0055 pinctrl-0 = <&led_mod_pins>;
0056
0057 led_mod: led_mod {
0058 label = "module:user";
0059 gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
0060 color = <LED_COLOR_ID_GREEN>;
0061 default-state = "off";
0062 panic-indicator;
0063 };
0064 };
0065 };
0066
0067 &mac_sw {
0068 pinctrl-names = "default", "sleep";
0069 pinctrl-0 = <ð_slave1_pins_default>;
0070 pinctrl-1 = <ð_slave1_pins_sleep>;
0071 status = "okay";
0072 };
0073
0074 &cpsw_port1 {
0075 phy-handle = <&phy0>;
0076 phy-mode = "rgmii-id";
0077 ti,dual-emac-pvid = <1>;
0078 };
0079
0080 &cpsw_port2 {
0081 status = "disabled";
0082 };
0083
0084 &davinci_mdio_sw {
0085 pinctrl-names = "default", "sleep";
0086 pinctrl-0 = <&mdio_pins_default>;
0087 pinctrl-1 = <&mdio_pins_sleep>;
0088
0089 phy0: ethernet-phy@4 {
0090 reg = <4>;
0091 };
0092 };
0093
0094 &elm {
0095 status = "okay";
0096 };
0097
0098 &gpmc {
0099 pinctrl-names = "default", "sleep";
0100 pinctrl-0 = <&nand_pins_default>;
0101 pinctrl-1 = <&nand_pins_sleep>;
0102 ranges = <0 0 0x8000000 0x1000000>;
0103 status = "okay";
0104
0105 nand0: nand@0,0 {
0106 compatible = "ti,omap2-nand";
0107 reg = <0 0 4>;
0108 interrupt-parent = <&gpmc>;
0109 interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE_NONE>;
0110 nand-bus-width = <8>;
0111 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;
0112 gpmc,device-width = <1>;
0113 gpmc,sync-clk-ps = <0>;
0114 gpmc,cs-on-ns = <0>;
0115 gpmc,cs-rd-off-ns = <44>;
0116 gpmc,cs-wr-off-ns = <44>;
0117 gpmc,adv-on-ns = <6>;
0118 gpmc,adv-rd-off-ns = <34>;
0119 gpmc,adv-wr-off-ns = <44>;
0120 gpmc,we-on-ns = <0>;
0121 gpmc,we-off-ns = <40>;
0122 gpmc,oe-on-ns = <0>;
0123 gpmc,oe-off-ns = <54>;
0124 gpmc,access-ns = <64>;
0125 gpmc,rd-cycle-ns = <82>;
0126 gpmc,wr-cycle-ns = <82>;
0127 gpmc,bus-turnaround-ns = <0>;
0128 gpmc,cycle2cycle-delay-ns = <0>;
0129 gpmc,clk-activation-ns = <0>;
0130 gpmc,wr-access-ns = <40>;
0131 gpmc,wr-data-mux-bus-ns = <0>;
0132 ti,elm-id = <&elm>;
0133 ti,nand-ecc-opt = "bch8";
0134 };
0135 };
0136
0137 &i2c0 {
0138 pinctrl-names = "default", "gpio", "sleep";
0139 pinctrl-0 = <&i2c0_pins_default>;
0140 pinctrl-1 = <&i2c0_pins_gpio>;
0141 pinctrl-2 = <&i2c0_pins_sleep>;
0142 clock-frequency = <400000>;
0143 scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0144 sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0145 status = "okay";
0146
0147 eeprom: eeprom@50 {
0148 compatible = "atmel,24c32";
0149 reg = <0x50>;
0150 pagesize = <32>;
0151 vcc-supply = <&vdd_mod>;
0152 };
0153 };
0154
0155 &rtc {
0156 clocks = <&clk32k>;
0157 clock-names = "ext-clk";
0158 system-power-controller;
0159 };
0160
0161 &am33xx_pinmux {
0162 mdio_pins_default: pinmux_mdio_pins_default {
0163 pinctrl-single,pins = <
0164 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data */
0165 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk */
0166 >;
0167 };
0168
0169 mdio_pins_sleep: pinmux_mdio_pins_sleep {
0170 pinctrl-single,pins = <
0171 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
0172 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
0173 >;
0174 };
0175
0176 eth_slave1_pins_default: pinmux_eth_slave1_pins_default {
0177 pinctrl-single,pins = <
0178 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tctl */
0179 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rctl */
0180 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td3 */
0181 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td2 */
0182 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td1 */
0183 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td0 */
0184 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tclk */
0185 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rclk */
0186 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd3 */
0187 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd2 */
0188 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd1 */
0189 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd0 */
0190 >;
0191 };
0192
0193 eth_slave1_pins_sleep: pinmux_eth_slave1_pins_sleep {
0194 pinctrl-single,pins = <
0195 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
0196 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
0197 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
0198 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
0199 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
0200 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
0201 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
0202 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
0203 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
0204 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
0205 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
0206 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
0207 >;
0208 };
0209
0210 i2c0_pins_default: pinmux_i2c0_pins_default {
0211 pinctrl-single,pins = <
0212 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SDA */
0213 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SCL */
0214 >;
0215 };
0216
0217 i2c0_pins_gpio: pinmux_i2c0_pins_gpio {
0218 pinctrl-single,pins = <
0219 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE7) /* gpio3[5] */
0220 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE7) /* gpio3[6] */
0221 >;
0222 };
0223
0224 i2c0_pins_sleep: pinmux_i2c0_pins_sleep {
0225 pinctrl-single,pins = <
0226 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE7)
0227 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE7)
0228 >;
0229 };
0230
0231 led_mod_pins: pinmux_led_mod_pins {
0232 pinctrl-single,pins = <
0233 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpio3[18] */
0234 >;
0235 };
0236
0237 nand_pins_default: pinmux_nand_pins_default {
0238 pinctrl-single,pins = <
0239 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0 */
0240 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1 */
0241 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2 */
0242 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3 */
0243 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4 */
0244 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5 */
0245 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6 */
0246 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7 */
0247 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0 */
0248 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio0[31] */
0249 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0 */
0250 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale */
0251 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren */
0252 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen */
0253 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle */
0254 >;
0255 };
0256
0257 nand_pins_sleep: pinmux_nand_pins_sleep {
0258 pinctrl-single,pins = <
0259 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
0260 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
0261 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
0262 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
0263 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE7)
0264 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE7)
0265 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE7)
0266 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE7)
0267 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)
0268 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)
0269 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT_PULLDOWN, MUX_MODE7)
0270 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7)
0271 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7)
0272 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT_PULLDOWN, MUX_MODE7)
0273 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7)
0274 >;
0275 };
0276 };
