0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2020 MOXA Inc. - https://www.moxa.com/
0004 *
0005 * Author: Johnson Chen <johnsonch.chen@moxa.com>
0006 */
0007
0008 #include "am33xx.dtsi"
0009
0010 / {
0011
0012 cpus {
0013 cpu@0 {
0014 cpu0-supply = <&vdd1_reg>;
0015 };
0016 };
0017
0018 vbat: vbat-regulator {
0019 compatible = "regulator-fixed";
0020 };
0021
0022 /* Power supply provides a fixed 3.3V @3A */
0023 vmmcsd_fixed: vmmcsd-regulator {
0024 compatible = "regulator-fixed";
0025 regulator-name = "vmmcsd_fixed";
0026 regulator-min-microvolt = <3300000>;
0027 regulator-max-microvolt = <3300000>;
0028 regulator-boot-on;
0029 };
0030
0031 buttons: push_button {
0032 compatible = "gpio-keys";
0033 };
0034
0035 };
0036
0037 &am33xx_pinmux {
0038 pinctrl-names = "default";
0039 pinctrl-0 = <&minipcie_pins>;
0040
0041 minipcie_pins: pinmux_minipcie {
0042 pinctrl-single,pins = <
0043 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */
0044 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */
0045 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/
0046 >;
0047 };
0048
0049 push_button_pins: pinmux_push_button {
0050 pinctrl-single,pins = <
0051 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */
0052 >;
0053 };
0054
0055 i2c0_pins: pinmux_i2c0_pins {
0056 pinctrl-single,pins = <
0057 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
0058 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
0059 >;
0060 };
0061
0062
0063 i2c1_pins: pinmux_i2c1_pins {
0064 pinctrl-single,pins = <
0065 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */
0066 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */
0067 >;
0068 };
0069
0070 uart0_pins: pinmux_uart0_pins {
0071 pinctrl-single,pins = <
0072 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
0073 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0074 >;
0075 };
0076
0077 uart1_pins: pinmux_uart1_pins {
0078 pinctrl-single,pins = <
0079 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
0080 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0081 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
0082 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
0083 >;
0084 };
0085
0086 uart2_pins: pinmux_uart2_pins {
0087 pinctrl-single,pins = <
0088 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */
0089 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */
0090 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */
0091 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */
0092 >;
0093 };
0094
0095 cpsw_default: cpsw_default {
0096 pinctrl-single,pins = <
0097 /* Slave 1 */
0098 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
0099 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)
0100 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
0101 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
0102 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
0103 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
0104 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
0105 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
0106
0107 /* Slave 2 */
0108 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */
0109 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */
0110 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */
0111 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */
0112 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */
0113 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */
0114 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */
0115 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */
0116
0117 >;
0118 };
0119
0120 davinci_mdio_default: davinci_mdio_default {
0121 pinctrl-single,pins = <
0122 /* MDIO */
0123 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
0124 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
0125 >;
0126 };
0127
0128 mmc0_pins_default: pinmux_mmc0_pins {
0129 pinctrl-single,pins = <
0130 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
0131 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
0132 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
0133 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
0134 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
0135 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
0136 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */
0137 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */
0138 >;
0139 };
0140
0141 mmc2_pins_default: pinmux_mmc2_pins {
0142 pinctrl-single,pins = <
0143 /* eMMC */
0144 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */
0145 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */
0146 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */
0147 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */
0148 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */
0149 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */
0150 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */
0151 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */
0152 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
0153 AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */
0154 >;
0155 };
0156
0157 spi0_pins: pinmux_spi0 {
0158 pinctrl-single,pins = <
0159 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
0160 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
0161 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
0162 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
0163 >;
0164 };
0165
0166 };
0167
0168 &uart0 {
0169 /* Console */
0170 status = "okay";
0171 pinctrl-names = "default";
0172 pinctrl-0 = <&uart0_pins>;
0173 };
0174
0175 &uart1 {
0176 /* UART 1 setting */
0177 status = "okay";
0178 pinctrl-names = "default";
0179 pinctrl-0 = <&uart1_pins>;
0180 };
0181
0182 &uart5 {
0183 /* UART 2 setting */
0184 status = "okay";
0185 pinctrl-names = "default";
0186 pinctrl-0 = <&uart2_pins>;
0187 };
0188
0189 &i2c0 {
0190 pinctrl-names = "default";
0191 pinctrl-0 = <&i2c0_pins>;
0192
0193 status = "okay";
0194 clock-frequency = <400000>;
0195
0196 tps: tps@2d {
0197 compatible = "ti,tps65910";
0198 reg = <0x2d>;
0199 };
0200
0201 eeprom: eeprom@50 {
0202 compatible = "atmel,24c16";
0203 pagesize = <16>;
0204 reg = <0x50>;
0205 };
0206
0207 rtc_wdt: rtc_wdt@68 {
0208 compatible = "dallas,ds1374";
0209 reg = <0x68>;
0210 };
0211 };
0212
0213 &i2c1 {
0214 pinctrl-names = "default";
0215 pinctrl-0 = <&i2c1_pins>;
0216
0217 status = "okay";
0218 clock-frequency = <400000>;
0219 gpio_xten: gpio_xten@27 {
0220 compatible = "nxp,pca9535";
0221 gpio-controller;
0222 #gpio-cells = <2>;
0223 reg = <0x27>;
0224 };
0225 };
0226
0227 &usb0 {
0228 dr_mode = "host";
0229 };
0230
0231 &usb1 {
0232 dr_mode = "host";
0233 };
0234
0235
0236 #include "tps65910.dtsi"
0237 &tps {
0238 vcc1-supply = <&vbat>;
0239 vcc2-supply = <&vbat>;
0240 vcc3-supply = <&vbat>;
0241 vcc4-supply = <&vbat>;
0242 vcc5-supply = <&vbat>;
0243 vcc6-supply = <&vbat>;
0244 vcc7-supply = <&vbat>;
0245 vccio-supply = <&vbat>;
0246
0247 regulators {
0248 vrtc_reg: regulator@0 {
0249 regulator-always-on;
0250 };
0251
0252 vio_reg: regulator@1 {
0253 regulator-always-on;
0254 };
0255
0256 vdd1_reg: regulator@2 {
0257 regulator-always-on;
0258 };
0259
0260 vdd2_reg: regulator@3 {
0261 regulator-always-on;
0262 };
0263
0264 vdd3_reg: regulator@4 {
0265 regulator-always-on;
0266 };
0267
0268 vdig1_reg: regulator@5 {
0269 regulator-always-on;
0270 };
0271
0272 vdig2_reg: regulator@6 {
0273 regulator-always-on;
0274 };
0275
0276 vpll_reg: regulator@7 {
0277 regulator-always-on;
0278 };
0279
0280 vdac_reg: regulator@8 {
0281 regulator-always-on;
0282 };
0283
0284 vaux1_reg: regulator@9 {
0285 regulator-always-on;
0286 };
0287
0288 vaux2_reg: regulator@10 {
0289 regulator-always-on;
0290 };
0291
0292 vaux33_reg: regulator@11 {
0293 regulator-always-on;
0294 };
0295
0296 vmmc_reg: regulator@12 {
0297 compatible = "regulator-fixed";
0298 regulator-name = "vmmc_reg";
0299 regulator-min-microvolt = <3300000>;
0300 regulator-max-microvolt = <3300000>;
0301 regulator-always-on;
0302 };
0303 };
0304 };
0305
0306 /* Power */
0307 &vbat {
0308 regulator-name = "vbat";
0309 regulator-min-microvolt = <5000000>;
0310 regulator-max-microvolt = <5000000>;
0311 };
0312
0313 &mac_sw {
0314 pinctrl-names = "default";
0315 pinctrl-0 = <&cpsw_default>;
0316 status = "okay";
0317 };
0318
0319 &davinci_mdio_sw {
0320 pinctrl-names = "default";
0321 pinctrl-0 = <&davinci_mdio_default>;
0322
0323 ethphy0: ethernet-phy@4 {
0324 reg = <4>;
0325 };
0326
0327 ethphy1: ethernet-phy@5 {
0328 reg = <5>;
0329 };
0330 };
0331
0332 &cpsw_port1 {
0333 phy-handle = <ðphy0>;
0334 phy-mode = "rmii";
0335 ti,dual-emac-pvid = <1>;
0336 };
0337
0338 &cpsw_port2 {
0339 phy-handle = <ðphy1>;
0340 phy-mode = "rmii";
0341 ti,dual-emac-pvid = <2>;
0342 };
0343
0344 &sham {
0345 status = "okay";
0346 };
0347
0348 &aes {
0349 status = "okay";
0350 };
0351
0352 &gpio0_target {
0353 ti,no-reset-on-init;
0354 };
0355
0356 &mmc1 {
0357 pinctrl-names = "default";
0358 vmmc-supply = <&vmmcsd_fixed>;
0359 bus-width = <4>;
0360 pinctrl-0 = <&mmc0_pins_default>;
0361 cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
0362 wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
0363 status = "okay";
0364 };
0365
0366 &mmc3 {
0367 dmas = <&edma_xbar 12 0 1
0368 &edma_xbar 13 0 2>;
0369 dma-names = "tx", "rx";
0370 pinctrl-names = "default";
0371 vmmc-supply = <&vmmcsd_fixed>;
0372 bus-width = <8>;
0373 pinctrl-0 = <&mmc2_pins_default>;
0374 ti,non-removable;
0375 status = "okay";
0376 };
0377
0378 &buttons {
0379 pinctrl-names = "default";
0380 pinctrl-0 = <&push_button_pins>;
0381
0382 button-0 {
0383 label = "push_button";
0384 linux,code = <0x100>;
0385 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
0386 };
0387 };
0388
0389 /* SPI Busses */
0390 &spi0 {
0391 status = "okay";
0392 pinctrl-names = "default";
0393 pinctrl-0 = <&spi0_pins>;
0394
0395 flash@0 {
0396 compatible = "mx25l6405d";
0397 spi-max-frequency = <40000000>;
0398
0399 reg = <0>;
0400 spi-cpol;
0401 spi-cpha;
0402 #address-cells = <1>;
0403 #size-cells = <1>;
0404
0405 /* reg : The partition's offset and size within the mtd bank. */
0406 partitions@0 {
0407 label = "MLO";
0408 reg = <0x0 0x80000>;
0409 };
0410
0411 partitions@1 {
0412 label = "U-Boot";
0413 reg = <0x80000 0x100000>;
0414 };
0415
0416 partitions@2 {
0417 label = "U-Boot Env";
0418 reg = <0x180000 0x20000>;
0419 };
0420 };
0421 };
