0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/
0004 *
0005 * Authors: SZ Lin (林上智) <sz.lin@moxa.com>
0006 * Wes Huang (黃淵河) <wes.huang@moxa.com>
0007 * Fero JD Zhou (周俊達) <FeroJD.Zhou@moxa.com>
0008 */
0009
0010 /dts-v1/;
0011
0012 #include "am335x-moxa-uc-2100-common.dtsi"
0013
0014 / {
0015 model = "Moxa UC-2101";
0016 compatible = "moxa,uc-2101", "ti,am33xx";
0017
0018 leds {
0019 compatible = "gpio-leds";
0020 led1 {
0021 label = "UC2100:GREEN:USER";
0022 gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
0023 default-state = "off";
0024 };
0025 };
0026 };
0027
0028 &am33xx_pinmux {
0029 pinctrl-names = "default";
0030
0031 cpsw_default: cpsw_default {
0032 pinctrl-single,pins = <
0033 /* Slave 1 */
0034 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
0035 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
0036 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */
0037 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
0038 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
0039 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
0040 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
0041 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
0042 >;
0043 };
0044
0045 spi1_pins: pinmux_spi1 {
0046 pinctrl-single,pins = <
0047 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* ecap0_in_pwm0_out.spi1_sclk */
0048 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart1_ctsn.spi1_cs0 */
0049 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_ctsn.spi1_d0 */
0050 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_rtsn.spi1_d1 */
0051 >;
0052 };
0053 };
0054
0055 &davinci_mdio_sw {
0056 phy0: ethernet-phy@4 {
0057 reg = <4>;
0058 };
0059 };
0060
0061 &cpsw_port1 {
0062 phy-handle = <&phy0>;
0063 phy-mode = "rmii";
0064 };
0065
0066 &cpsw_port2 {
0067 status = "disabled";
0068 };
