0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2014 NovaTech LLC - https://www.novatechweb.com
0004 */
0005 /dts-v1/;
0006
0007 #include "am33xx.dtsi"
0008
0009 / {
0010 model = "NovaTech OrionLXm";
0011 compatible = "novatech,am335x-lxm", "ti,am33xx";
0012
0013 cpus {
0014 cpu@0 {
0015 cpu0-supply = <&vdd1_reg>;
0016 };
0017 };
0018
0019 memory@80000000 {
0020 device_type = "memory";
0021 reg = <0x80000000 0x20000000>; /* 512 MB */
0022 };
0023
0024 /* Power supply provides a fixed 5V @2A */
0025 vbat: fixedregulator0 {
0026 compatible = "regulator-fixed";
0027 regulator-name = "vbat";
0028 regulator-min-microvolt = <5000000>;
0029 regulator-max-microvolt = <5000000>;
0030 regulator-boot-on;
0031 };
0032
0033 /* Power supply provides a fixed 3.3V @3A */
0034 vmmcsd_fixed: fixedregulator1 {
0035 compatible = "regulator-fixed";
0036 regulator-name = "vmmcsd_fixed";
0037 regulator-min-microvolt = <3300000>;
0038 regulator-max-microvolt = <3300000>;
0039 regulator-boot-on;
0040 };
0041 };
0042
0043 &am33xx_pinmux {
0044 mmc1_pins: pinmux_mmc1_pins {
0045 pinctrl-single,pins = <
0046 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
0047 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
0048 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
0049 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
0050 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
0051 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
0052 >;
0053 };
0054
0055 i2c0_pins: pinmux_i2c0_pins {
0056 pinctrl-single,pins = <
0057 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
0058 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
0059 >;
0060 };
0061
0062 cpsw_default: cpsw_default {
0063 pinctrl-single,pins = <
0064 /* Slave 1 */
0065 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */
0066 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_crs_dv */
0067 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rxer */
0068 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_txen */
0069 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td1 */
0070 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td0 */
0071 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd1 */
0072 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd0 */
0073 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
0074
0075 /* Slave 2 */
0076 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */
0077 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */
0078 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */
0079 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */
0080 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */
0081 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */
0082 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */
0083 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */
0084 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */
0085 >;
0086 };
0087
0088 cpsw_sleep: cpsw_sleep {
0089 pinctrl-single,pins = <
0090 /* Slave 1 reset value */
0091 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */
0092 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_crs_dv */
0093 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rxer */
0094 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_txen */
0095 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td1 */
0096 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td0 */
0097 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd1 */
0098 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd0 */
0099 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk */
0100
0101 /* Slave 2 reset value*/
0102 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_txen */
0103 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td1 */
0104 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td0 */
0105 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd1 */
0106 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd0 */
0107 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_crs_dv */
0108 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rxer */
0109 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */
0110 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_refclk */
0111 >;
0112 };
0113
0114 davinci_mdio_default: davinci_mdio_default {
0115 pinctrl-single,pins = <
0116 /* MDIO */
0117 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
0118 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
0119 >;
0120 };
0121
0122 davinci_mdio_sleep: davinci_mdio_sleep {
0123 pinctrl-single,pins = <
0124 /* MDIO reset value */
0125 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
0126 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
0127 >;
0128 };
0129
0130 emmc_pins: pinmux_emmc_pins {
0131 pinctrl-single,pins = <
0132 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
0133 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
0134 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
0135 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
0136 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
0137 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
0138 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
0139 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
0140 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
0141 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
0142 >;
0143 };
0144
0145 uart0_pins: pinmux_uart0_pins {
0146 pinctrl-single,pins = <
0147 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
0148 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0149 >;
0150 };
0151 };
0152
0153 &i2c0 {
0154 pinctrl-names = "default";
0155 pinctrl-0 = <&i2c0_pins>;
0156
0157 status = "okay";
0158 clock-frequency = <400000>;
0159
0160 serial_config1: serial_config1@20 {
0161 compatible = "nxp,pca9539";
0162 reg = <0x20>;
0163 gpio-controller;
0164 #gpio-cells = <2>;
0165 };
0166
0167 serial_config2: serial_config2@21 {
0168 compatible = "nxp,pca9539";
0169 reg = <0x21>;
0170 gpio-controller;
0171 #gpio-cells = <2>;
0172 };
0173
0174 tps: tps@2d {
0175 compatible = "ti,tps65910";
0176 reg = <0x2d>;
0177 };
0178 };
0179
0180 /include/ "tps65910.dtsi"
0181
0182 &tps {
0183 vcc1-supply = <&vbat>;
0184 vcc2-supply = <&vbat>;
0185 vcc3-supply = <&vbat>;
0186 vcc4-supply = <&vbat>;
0187 vcc5-supply = <&vbat>;
0188 vcc6-supply = <&vbat>;
0189 vcc7-supply = <&vbat>;
0190 vccio-supply = <&vbat>;
0191
0192 regulators {
0193 /* vrtc - unused */
0194
0195 vio_reg: regulator@1 {
0196 regulator-name = "vio_1v5,ddr";
0197 regulator-min-microvolt = <1500000>;
0198 regulator-max-microvolt = <1500000>;
0199 regulator-boot-on;
0200 regulator-always-on;
0201 };
0202
0203 vdd1_reg: regulator@2 {
0204 regulator-name = "vdd1,mpu";
0205 regulator-min-microvolt = <600000>;
0206 regulator-max-microvolt = <1500000>;
0207 regulator-boot-on;
0208 regulator-always-on;
0209 };
0210
0211 vdd2_reg: regulator@3 {
0212 regulator-name = "vdd2_1v1,core";
0213 regulator-min-microvolt = <1100000>;
0214 regulator-max-microvolt = <1100000>;
0215 regulator-boot-on;
0216 regulator-always-on;
0217 };
0218
0219 /* vdd3 - unused */
0220
0221 /* vdig1 - unused */
0222
0223 vdig2_reg: regulator@6 {
0224 regulator-name = "vdig2_1v8,vdds_pll";
0225 regulator-min-microvolt = <1800000>;
0226 regulator-max-microvolt = <1800000>;
0227 regulator-boot-on;
0228 regulator-always-on;
0229 };
0230
0231 /* vpll - unused */
0232
0233 vdac_reg: regulator@8 {
0234 regulator-name = "vdac_1v8,vdds";
0235 regulator-min-microvolt = <1800000>;
0236 regulator-max-microvolt = <1800000>;
0237 regulator-boot-on;
0238 regulator-always-on;
0239 };
0240
0241 vaux1_reg: regulator@9 {
0242 regulator-name = "vaux1_1v8,usb";
0243 regulator-min-microvolt = <1800000>;
0244 regulator-max-microvolt = <1800000>;
0245 regulator-boot-on;
0246 regulator-always-on;
0247 };
0248
0249 vaux2_reg: regulator@10 {
0250 regulator-name = "vaux2_3v3,io";
0251 regulator-min-microvolt = <3300000>;
0252 regulator-max-microvolt = <3300000>;
0253 regulator-boot-on;
0254 regulator-always-on;
0255 };
0256
0257 vaux33_reg: regulator@11 {
0258 regulator-name = "vaux33_3v3,usb";
0259 regulator-min-microvolt = <3300000>;
0260 regulator-max-microvolt = <3300000>;
0261 regulator-boot-on;
0262 regulator-always-on;
0263 };
0264
0265 vmmc_reg: regulator@12 {
0266 regulator-name = "vmmc_3v3,io";
0267 regulator-min-microvolt = <3300000>;
0268 regulator-max-microvolt = <3300000>;
0269 regulator-boot-on;
0270 regulator-always-on;
0271 };
0272 };
0273 };
0274
0275 &sham {
0276 status = "okay";
0277 };
0278
0279 &aes {
0280 status = "okay";
0281 };
0282
0283 &uart0 {
0284 pinctrl-names = "default";
0285 pinctrl-0 = <&uart0_pins>;
0286
0287 status = "okay";
0288 };
0289
0290 &usb0 {
0291 dr_mode = "host";
0292 };
0293
0294 &usb1 {
0295 dr_mode = "host";
0296 };
0297
0298 &cpsw_port1 {
0299 phy-handle = <ðphy0>;
0300 phy-mode = "rmii";
0301 ti,dual-emac-pvid = <2>;
0302 };
0303
0304 &cpsw_port2 {
0305 phy-handle = <ðphy1>;
0306 phy-mode = "rmii";
0307 ti,dual-emac-pvid = <3>;
0308 };
0309
0310 &mac_sw {
0311 pinctrl-names = "default", "sleep";
0312 pinctrl-0 = <&cpsw_default>;
0313 pinctrl-1 = <&cpsw_sleep>;
0314 status = "okay";
0315 };
0316
0317 &davinci_mdio_sw {
0318 pinctrl-names = "default", "sleep";
0319 pinctrl-0 = <&davinci_mdio_default>;
0320 pinctrl-1 = <&davinci_mdio_sleep>;
0321
0322 ethphy0: ethernet-phy@5 {
0323 reg = <5>;
0324 };
0325
0326 ethphy1: ethernet-phy@4 {
0327 reg = <4>;
0328 };
0329 };
0330
0331 &mmc1 {
0332 pinctrl-names = "default";
0333 pinctrl-0 = <&mmc1_pins>;
0334 vmmc-supply = <&vmmcsd_fixed>;
0335 bus-width = <4>;
0336 status = "okay";
0337 };
0338
0339 &mmc2 {
0340 pinctrl-names = "default";
0341 pinctrl-0 = <&emmc_pins>;
0342 vmmc-supply = <&vmmcsd_fixed>;
0343 bus-width = <8>;
0344 non-removable;
0345 status = "okay";
0346 };
0347
