0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
0004 */
0005 /dts-v1/;
0006
0007 #include "am33xx.dtsi"
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009
0010 / {
0011 model = "TI AM335x EVM";
0012 compatible = "ti,am335x-evm", "ti,am33xx";
0013
0014 cpus {
0015 cpu@0 {
0016 cpu0-supply = <&vdd1_reg>;
0017 };
0018 };
0019
0020 memory@80000000 {
0021 device_type = "memory";
0022 reg = <0x80000000 0x10000000>; /* 256 MB */
0023 };
0024
0025 chosen {
0026 stdout-path = &uart0;
0027 };
0028
0029 vbat: fixedregulator0 {
0030 compatible = "regulator-fixed";
0031 regulator-name = "vbat";
0032 regulator-min-microvolt = <5000000>;
0033 regulator-max-microvolt = <5000000>;
0034 regulator-boot-on;
0035 };
0036
0037 lis3_reg: fixedregulator1 {
0038 compatible = "regulator-fixed";
0039 regulator-name = "lis3_reg";
0040 regulator-boot-on;
0041 };
0042
0043 wlan_en_reg: fixedregulator2 {
0044 compatible = "regulator-fixed";
0045 regulator-name = "wlan-en-regulator";
0046 regulator-min-microvolt = <1800000>;
0047 regulator-max-microvolt = <1800000>;
0048
0049 /* WLAN_EN GPIO for this board - Bank1, pin16 */
0050 gpio = <&gpio1 16 0>;
0051
0052 /* WLAN card specific delay */
0053 startup-delay-us = <70000>;
0054 enable-active-high;
0055 };
0056
0057 /* TPS79501 */
0058 v1_8d_reg: fixedregulator-v1_8d {
0059 compatible = "regulator-fixed";
0060 regulator-name = "v1_8d";
0061 vin-supply = <&vbat>;
0062 regulator-min-microvolt = <1800000>;
0063 regulator-max-microvolt = <1800000>;
0064 };
0065
0066 /* TPS79501 */
0067 v3_3d_reg: fixedregulator-v3_3d {
0068 compatible = "regulator-fixed";
0069 regulator-name = "v3_3d";
0070 vin-supply = <&vbat>;
0071 regulator-min-microvolt = <3300000>;
0072 regulator-max-microvolt = <3300000>;
0073 };
0074
0075 matrix_keypad: matrix_keypad0 {
0076 compatible = "gpio-matrix-keypad";
0077 debounce-delay-ms = <5>;
0078 col-scan-delay-us = <2>;
0079
0080 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
0081 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
0082 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
0083
0084 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
0085 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
0086
0087 linux,keymap = <0x0000008b /* MENU */
0088 0x0100009e /* BACK */
0089 0x02000069 /* LEFT */
0090 0x0001006a /* RIGHT */
0091 0x0101001c /* ENTER */
0092 0x0201006c>; /* DOWN */
0093 };
0094
0095 gpio_keys: volume-keys {
0096 compatible = "gpio-keys";
0097 autorepeat;
0098
0099 switch-9 {
0100 label = "volume-up";
0101 linux,code = <115>;
0102 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
0103 wakeup-source;
0104 };
0105
0106 switch-10 {
0107 label = "volume-down";
0108 linux,code = <114>;
0109 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
0110 wakeup-source;
0111 };
0112 };
0113
0114 backlight: backlight {
0115 compatible = "pwm-backlight";
0116 pwms = <&ecap0 0 50000 0>;
0117 brightness-levels = <0 51 53 56 62 75 101 152 255>;
0118 default-brightness-level = <8>;
0119 };
0120
0121 panel {
0122 compatible = "tfc,s9700rtwv43tr-01b";
0123
0124 pinctrl-names = "default";
0125 pinctrl-0 = <&lcd_pins_s0>;
0126 backlight = <&backlight>;
0127
0128 port {
0129 panel_0: endpoint@0 {
0130 remote-endpoint = <&lcdc_0>;
0131 };
0132 };
0133 };
0134
0135 sound {
0136 compatible = "simple-audio-card";
0137 simple-audio-card,name = "AM335x-EVM";
0138 simple-audio-card,widgets =
0139 "Headphone", "Headphone Jack",
0140 "Line", "Line In";
0141 simple-audio-card,routing =
0142 "Headphone Jack", "HPLOUT",
0143 "Headphone Jack", "HPROUT",
0144 "LINE1L", "Line In",
0145 "LINE1R", "Line In";
0146 simple-audio-card,format = "dsp_b";
0147 simple-audio-card,bitclock-master = <&sound_master>;
0148 simple-audio-card,frame-master = <&sound_master>;
0149 simple-audio-card,bitclock-inversion;
0150
0151 simple-audio-card,cpu {
0152 sound-dai = <&mcasp1>;
0153 };
0154
0155 sound_master: simple-audio-card,codec {
0156 sound-dai = <&tlv320aic3106>;
0157 system-clock-frequency = <12000000>;
0158 };
0159 };
0160 };
0161
0162 &am33xx_pinmux {
0163 pinctrl-names = "default";
0164 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
0165
0166 matrix_keypad_s0: matrix_keypad_s0 {
0167 pinctrl-single,pins = <
0168 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */
0169 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a6.gpio1_22 */
0170 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a9.gpio1_25 */
0171 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a10.gpio1_26 */
0172 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */
0173 >;
0174 };
0175
0176 volume_keys_s0: volume_keys_s0 {
0177 pinctrl-single,pins = <
0178 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_sclk.gpio0_2 */
0179 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_d0.gpio0_3 */
0180 >;
0181 };
0182
0183 i2c0_pins: pinmux_i2c0_pins {
0184 pinctrl-single,pins = <
0185 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */
0186 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */
0187 >;
0188 };
0189
0190 i2c1_pins: pinmux_i2c1_pins {
0191 pinctrl-single,pins = <
0192 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */
0193 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */
0194 >;
0195 };
0196
0197 uart0_pins: pinmux_uart0_pins {
0198 pinctrl-single,pins = <
0199 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
0200 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0201 >;
0202 };
0203
0204 uart1_pins: pinmux_uart1_pins {
0205 pinctrl-single,pins = <
0206 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
0207 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0208 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
0209 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0210 >;
0211 };
0212
0213 clkout2_pin: pinmux_clkout2_pin {
0214 pinctrl-single,pins = <
0215 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */
0216 >;
0217 };
0218
0219 nandflash_pins_s0: nandflash_pins_s0 {
0220 pinctrl-single,pins = <
0221 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
0222 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
0223 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
0224 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
0225 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
0226 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
0227 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
0228 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
0229 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
0230 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
0231 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
0232 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
0233 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
0234 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
0235 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
0236 >;
0237 };
0238
0239 ecap0_pins: backlight_pins {
0240 pinctrl-single,pins = <
0241 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0)
0242 >;
0243 };
0244
0245 cpsw_default: cpsw_default {
0246 pinctrl-single,pins = <
0247 /* Slave 1 */
0248 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */
0249 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
0250 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
0251 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
0252 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
0253 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
0254 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
0255 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
0256 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
0257 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
0258 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
0259 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
0260 >;
0261 };
0262
0263 cpsw_sleep: cpsw_sleep {
0264 pinctrl-single,pins = <
0265 /* Slave 1 reset value */
0266 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
0267 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
0268 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
0269 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
0270 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
0271 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
0272 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
0273 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
0274 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
0275 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
0276 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
0277 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
0278 >;
0279 };
0280
0281 davinci_mdio_default: davinci_mdio_default {
0282 pinctrl-single,pins = <
0283 /* MDIO */
0284 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
0285 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
0286 >;
0287 };
0288
0289 davinci_mdio_sleep: davinci_mdio_sleep {
0290 pinctrl-single,pins = <
0291 /* MDIO reset value */
0292 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
0293 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
0294 >;
0295 };
0296
0297 mmc1_pins: pinmux_mmc1_pins {
0298 pinctrl-single,pins = <
0299 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */
0300 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
0301 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
0302 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
0303 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
0304 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
0305 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
0306 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */
0307 >;
0308 };
0309
0310 mmc3_pins: pinmux_mmc3_pins {
0311 pinctrl-single,pins = <
0312 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
0313 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
0314 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
0315 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
0316 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
0317 AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
0318 >;
0319 };
0320
0321 wlan_pins: pinmux_wlan_pins {
0322 pinctrl-single,pins = <
0323 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a0.gpio1_16 */
0324 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
0325 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
0326 >;
0327 };
0328
0329 lcd_pins_s0: lcd_pins_s0 {
0330 pinctrl-single,pins = <
0331 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */
0332 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */
0333 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */
0334 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */
0335 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */
0336 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */
0337 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */
0338 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */
0339 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
0340 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
0341 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
0342 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
0343 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
0344 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
0345 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
0346 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
0347 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
0348 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
0349 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
0350 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
0351 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
0352 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
0353 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
0354 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
0355 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
0356 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
0357 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
0358 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
0359 >;
0360 };
0361
0362 mcasp1_pins: mcasp1_pins {
0363 pinctrl-single,pins = <
0364 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
0365 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
0366 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
0367 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
0368 >;
0369 };
0370
0371 mcasp1_pins_sleep: mcasp1_pins_sleep {
0372 pinctrl-single,pins = <
0373 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
0374 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
0375 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
0376 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
0377 >;
0378 };
0379
0380 dcan1_pins_default: dcan1_pins_default {
0381 pinctrl-single,pins = <
0382 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
0383 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
0384 >;
0385 };
0386 };
0387
0388 &uart0 {
0389 pinctrl-names = "default";
0390 pinctrl-0 = <&uart0_pins>;
0391
0392 status = "okay";
0393 };
0394
0395 &uart1 {
0396 pinctrl-names = "default";
0397 pinctrl-0 = <&uart1_pins>;
0398
0399 status = "okay";
0400 };
0401
0402 &i2c0 {
0403 pinctrl-names = "default";
0404 pinctrl-0 = <&i2c0_pins>;
0405
0406 status = "okay";
0407 clock-frequency = <400000>;
0408
0409 tps: tps@2d {
0410 reg = <0x2d>;
0411 };
0412 };
0413
0414 &usb1 {
0415 dr_mode = "host";
0416 };
0417
0418 &i2c1 {
0419 pinctrl-names = "default";
0420 pinctrl-0 = <&i2c1_pins>;
0421
0422 status = "okay";
0423 clock-frequency = <100000>;
0424
0425 lis331dlh: lis331dlh@18 {
0426 compatible = "st,lis331dlh", "st,lis3lv02d";
0427 reg = <0x18>;
0428 Vdd-supply = <&lis3_reg>;
0429 Vdd_IO-supply = <&lis3_reg>;
0430
0431 st,click-single-x;
0432 st,click-single-y;
0433 st,click-single-z;
0434 st,click-thresh-x = <10>;
0435 st,click-thresh-y = <10>;
0436 st,click-thresh-z = <10>;
0437 st,irq1-click;
0438 st,irq2-click;
0439 st,wakeup-x-lo;
0440 st,wakeup-x-hi;
0441 st,wakeup-y-lo;
0442 st,wakeup-y-hi;
0443 st,wakeup-z-lo;
0444 st,wakeup-z-hi;
0445 st,min-limit-x = <120>;
0446 st,min-limit-y = <120>;
0447 st,min-limit-z = <140>;
0448 st,max-limit-x = <550>;
0449 st,max-limit-y = <550>;
0450 st,max-limit-z = <750>;
0451 };
0452
0453 tsl2550: tsl2550@39 {
0454 compatible = "taos,tsl2550";
0455 reg = <0x39>;
0456 };
0457
0458 tmp275: tmp275@48 {
0459 compatible = "ti,tmp275";
0460 reg = <0x48>;
0461 };
0462
0463 tlv320aic3106: tlv320aic3106@1b {
0464 #sound-dai-cells = <0>;
0465 compatible = "ti,tlv320aic3106";
0466 reg = <0x1b>;
0467 status = "okay";
0468
0469 /* Regulators */
0470 AVDD-supply = <&v3_3d_reg>;
0471 IOVDD-supply = <&v3_3d_reg>;
0472 DRVDD-supply = <&v3_3d_reg>;
0473 DVDD-supply = <&v1_8d_reg>;
0474 };
0475 };
0476
0477 &lcdc {
0478 status = "okay";
0479
0480 blue-and-red-wiring = "crossed";
0481
0482 port {
0483 lcdc_0: endpoint@0 {
0484 remote-endpoint = <&panel_0>;
0485 };
0486 };
0487 };
0488
0489 &elm {
0490 status = "okay";
0491 };
0492
0493 &epwmss0 {
0494 status = "okay";
0495
0496 ecap0: pwm@100 {
0497 status = "okay";
0498 pinctrl-names = "default";
0499 pinctrl-0 = <&ecap0_pins>;
0500 };
0501 };
0502
0503 &gpmc {
0504 status = "okay";
0505 pinctrl-names = "default";
0506 pinctrl-0 = <&nandflash_pins_s0>;
0507 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
0508 nand@0,0 {
0509 compatible = "ti,omap2-nand";
0510 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
0511 interrupt-parent = <&gpmc>;
0512 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
0513 <1 IRQ_TYPE_NONE>; /* termcount */
0514 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
0515 ti,nand-xfer-type = "prefetch-dma";
0516 ti,nand-ecc-opt = "bch8";
0517 ti,elm-id = <&elm>;
0518 nand-bus-width = <8>;
0519 gpmc,device-width = <1>;
0520 gpmc,sync-clk-ps = <0>;
0521 gpmc,cs-on-ns = <0>;
0522 gpmc,cs-rd-off-ns = <44>;
0523 gpmc,cs-wr-off-ns = <44>;
0524 gpmc,adv-on-ns = <6>;
0525 gpmc,adv-rd-off-ns = <34>;
0526 gpmc,adv-wr-off-ns = <44>;
0527 gpmc,we-on-ns = <0>;
0528 gpmc,we-off-ns = <40>;
0529 gpmc,oe-on-ns = <0>;
0530 gpmc,oe-off-ns = <54>;
0531 gpmc,access-ns = <64>;
0532 gpmc,rd-cycle-ns = <82>;
0533 gpmc,wr-cycle-ns = <82>;
0534 gpmc,bus-turnaround-ns = <0>;
0535 gpmc,cycle2cycle-delay-ns = <0>;
0536 gpmc,clk-activation-ns = <0>;
0537 gpmc,wr-access-ns = <40>;
0538 gpmc,wr-data-mux-bus-ns = <0>;
0539 /* MTD partition table */
0540 /* All SPL-* partitions are sized to minimal length
0541 * which can be independently programmable. For
0542 * NAND flash this is equal to size of erase-block */
0543 #address-cells = <1>;
0544 #size-cells = <1>;
0545 partition@0 {
0546 label = "NAND.SPL";
0547 reg = <0x00000000 0x000020000>;
0548 };
0549 partition@1 {
0550 label = "NAND.SPL.backup1";
0551 reg = <0x00020000 0x00020000>;
0552 };
0553 partition@2 {
0554 label = "NAND.SPL.backup2";
0555 reg = <0x00040000 0x00020000>;
0556 };
0557 partition@3 {
0558 label = "NAND.SPL.backup3";
0559 reg = <0x00060000 0x00020000>;
0560 };
0561 partition@4 {
0562 label = "NAND.u-boot-spl-os";
0563 reg = <0x00080000 0x00040000>;
0564 };
0565 partition@5 {
0566 label = "NAND.u-boot";
0567 reg = <0x000C0000 0x00100000>;
0568 };
0569 partition@6 {
0570 label = "NAND.u-boot-env";
0571 reg = <0x001C0000 0x00020000>;
0572 };
0573 partition@7 {
0574 label = "NAND.u-boot-env.backup1";
0575 reg = <0x001E0000 0x00020000>;
0576 };
0577 partition@8 {
0578 label = "NAND.kernel";
0579 reg = <0x00200000 0x00800000>;
0580 };
0581 partition@9 {
0582 label = "NAND.file-system";
0583 reg = <0x00A00000 0x0F600000>;
0584 };
0585 };
0586 };
0587
0588 #include "tps65910.dtsi"
0589
0590 &mcasp1 {
0591 #sound-dai-cells = <0>;
0592 pinctrl-names = "default", "sleep";
0593 pinctrl-0 = <&mcasp1_pins>;
0594 pinctrl-1 = <&mcasp1_pins_sleep>;
0595
0596 status = "okay";
0597
0598 op-mode = <0>; /* MCASP_IIS_MODE */
0599 tdm-slots = <2>;
0600 /* 4 serializers */
0601 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0602 0 0 1 2
0603 >;
0604 tx-num-evt = <32>;
0605 rx-num-evt = <32>;
0606 };
0607
0608 &tps {
0609 vcc1-supply = <&vbat>;
0610 vcc2-supply = <&vbat>;
0611 vcc3-supply = <&vbat>;
0612 vcc4-supply = <&vbat>;
0613 vcc5-supply = <&vbat>;
0614 vcc6-supply = <&vbat>;
0615 vcc7-supply = <&vbat>;
0616 vccio-supply = <&vbat>;
0617
0618 regulators {
0619 vrtc_reg: regulator@0 {
0620 regulator-always-on;
0621 };
0622
0623 vio_reg: regulator@1 {
0624 regulator-always-on;
0625 };
0626
0627 vdd1_reg: regulator@2 {
0628 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
0629 regulator-name = "vdd_mpu";
0630 regulator-min-microvolt = <912500>;
0631 regulator-max-microvolt = <1351500>;
0632 regulator-boot-on;
0633 regulator-always-on;
0634 };
0635
0636 vdd2_reg: regulator@3 {
0637 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
0638 regulator-name = "vdd_core";
0639 regulator-min-microvolt = <912500>;
0640 regulator-max-microvolt = <1150000>;
0641 regulator-boot-on;
0642 regulator-always-on;
0643 };
0644
0645 vdd3_reg: regulator@4 {
0646 regulator-always-on;
0647 };
0648
0649 vdig1_reg: regulator@5 {
0650 regulator-always-on;
0651 };
0652
0653 vdig2_reg: regulator@6 {
0654 regulator-always-on;
0655 };
0656
0657 vpll_reg: regulator@7 {
0658 regulator-always-on;
0659 };
0660
0661 vdac_reg: regulator@8 {
0662 regulator-always-on;
0663 };
0664
0665 vaux1_reg: regulator@9 {
0666 regulator-always-on;
0667 };
0668
0669 vaux2_reg: regulator@10 {
0670 regulator-always-on;
0671 };
0672
0673 vaux33_reg: regulator@11 {
0674 regulator-always-on;
0675 };
0676
0677 vmmc_reg: regulator@12 {
0678 regulator-min-microvolt = <1800000>;
0679 regulator-max-microvolt = <3300000>;
0680 regulator-always-on;
0681 };
0682 };
0683 };
0684
0685 &mac_sw {
0686 pinctrl-names = "default", "sleep";
0687 pinctrl-0 = <&cpsw_default>;
0688 pinctrl-1 = <&cpsw_sleep>;
0689 status = "okay";
0690 };
0691
0692 &davinci_mdio_sw {
0693 pinctrl-names = "default", "sleep";
0694 pinctrl-0 = <&davinci_mdio_default>;
0695 pinctrl-1 = <&davinci_mdio_sleep>;
0696
0697 ethphy0: ethernet-phy@0 {
0698 reg = <0>;
0699 };
0700 };
0701
0702 &cpsw_port1 {
0703 phy-handle = <ðphy0>;
0704 phy-mode = "rgmii-id";
0705 ti,dual-emac-pvid = <1>;
0706 };
0707
0708 &cpsw_port2 {
0709 status = "disabled";
0710 };
0711
0712 &tscadc {
0713 status = "okay";
0714 tsc {
0715 ti,wires = <4>;
0716 ti,x-plate-resistance = <200>;
0717 ti,coordinate-readouts = <5>;
0718 ti,wire-config = <0x00 0x11 0x22 0x33>;
0719 ti,charge-delay = <0x400>;
0720 };
0721
0722 adc {
0723 ti,adc-channels = <4 5 6 7>;
0724 };
0725 };
0726
0727 &mmc1 {
0728 status = "okay";
0729 vmmc-supply = <&vmmc_reg>;
0730 bus-width = <4>;
0731 pinctrl-names = "default";
0732 pinctrl-0 = <&mmc1_pins>;
0733 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
0734 };
0735
0736 &mmc3 {
0737 /* these are on the crossbar and are outlined in the
0738 xbar-event-map element */
0739 dmas = <&edma_xbar 12 0 1
0740 &edma_xbar 13 0 2>;
0741 dma-names = "tx", "rx";
0742 status = "okay";
0743 vmmc-supply = <&wlan_en_reg>;
0744 bus-width = <4>;
0745 pinctrl-names = "default";
0746 pinctrl-0 = <&mmc3_pins &wlan_pins>;
0747 non-removable;
0748 cap-power-off-card;
0749 keep-power-in-suspend;
0750
0751 #address-cells = <1>;
0752 #size-cells = <0>;
0753 wlcore: wlcore@0 {
0754 compatible = "ti,wl1835";
0755 reg = <2>;
0756 interrupt-parent = <&gpio3>;
0757 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
0758 };
0759 };
0760
0761 &sham {
0762 status = "okay";
0763 };
0764
0765 &aes {
0766 status = "okay";
0767 };
0768
0769 &dcan1 {
0770 status = "disabled"; /* Enable only if Profile 1 is selected */
0771 pinctrl-names = "default";
0772 pinctrl-0 = <&dcan1_pins_default>;
0773 };
0774
0775 &rtc {
0776 clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
0777 clock-names = "ext-clk", "int-clk";
0778 };
0779
0780 &pruss_tm {
0781 status = "okay";
0782 };
0783
0784 &wkup_m3_ipc {
0785 firmware-name = "am335x-evm-scale-data.bin";
0786 };
