0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
0004 * Author: Rostislav Lisovy <lisovy@jablotron.cz>
0005 */
0006 #include "am33xx.dtsi"
0007 #include <dt-bindings/interrupt-controller/irq.h>
0008
0009 / {
0010 model = "Grinn AM335x ChiliSOM";
0011 compatible = "grinn,am335x-chilisom", "ti,am33xx";
0012
0013 cpus {
0014 cpu@0 {
0015 cpu0-supply = <&dcdc2_reg>;
0016 };
0017 };
0018
0019 memory@80000000 {
0020 device_type = "memory";
0021 reg = <0x80000000 0x20000000>; /* 512 MB */
0022 };
0023 };
0024
0025 &am33xx_pinmux {
0026 pinctrl-names = "default";
0027
0028 i2c0_pins: pinmux_i2c0_pins {
0029 pinctrl-single,pins = <
0030 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
0031 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
0032 >;
0033 };
0034
0035 nandflash_pins: nandflash_pins {
0036 pinctrl-single,pins = <
0037 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
0038 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
0039 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE0)
0040 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE0)
0041 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE0)
0042 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE0)
0043 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE0)
0044 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE0)
0045
0046 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
0047 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE0)
0048 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLUP, MUX_MODE0)
0049 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLUP, MUX_MODE0)
0050 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT_PULLUP, MUX_MODE0)
0051 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT_PULLUP, MUX_MODE0)
0052 >;
0053 };
0054 };
0055
0056 &i2c0 {
0057 pinctrl-names = "default";
0058 pinctrl-0 = <&i2c0_pins>;
0059
0060 status = "okay";
0061 clock-frequency = <400000>;
0062
0063 tps: tps@24 {
0064 reg = <0x24>;
0065 };
0066
0067 };
0068
0069 /include/ "tps65217.dtsi"
0070
0071 &tps {
0072 regulators {
0073 dcdc1_reg: regulator@0 {
0074 regulator-name = "vdds_dpr";
0075 regulator-always-on;
0076 };
0077
0078 dcdc2_reg: regulator@1 {
0079 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
0080 regulator-name = "vdd_mpu";
0081 regulator-min-microvolt = <925000>;
0082 regulator-max-microvolt = <1325000>;
0083 regulator-boot-on;
0084 regulator-always-on;
0085 };
0086
0087 dcdc3_reg: regulator@2 {
0088 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
0089 regulator-name = "vdd_core";
0090 regulator-min-microvolt = <925000>;
0091 regulator-max-microvolt = <1150000>;
0092 regulator-boot-on;
0093 regulator-always-on;
0094 };
0095
0096 ldo1_reg: regulator@3 {
0097 regulator-name = "vio,vrtc,vdds";
0098 regulator-boot-on;
0099 regulator-always-on;
0100 };
0101
0102 ldo2_reg: regulator@4 {
0103 regulator-name = "vdd_3v3aux";
0104 regulator-boot-on;
0105 regulator-always-on;
0106 };
0107
0108 ldo3_reg: regulator@5 {
0109 regulator-name = "vdd_1v8";
0110 regulator-boot-on;
0111 regulator-always-on;
0112 };
0113
0114 ldo4_reg: regulator@6 {
0115 regulator-name = "vdd_3v3d";
0116 regulator-boot-on;
0117 regulator-always-on;
0118 };
0119 };
0120 };
0121
0122 &rtc {
0123 system-power-controller;
0124
0125 pinctrl-0 = <&ext_wakeup>;
0126 pinctrl-names = "default";
0127
0128 ext_wakeup: ext-wakeup {
0129 pins = "ext_wakeup0";
0130 input-enable;
0131 };
0132 };
0133
0134 /* NAND Flash */
0135 &elm {
0136 status = "okay";
0137 };
0138
0139 &gpmc {
0140 status = "okay";
0141 pinctrl-names = "default";
0142 pinctrl-0 = <&nandflash_pins>;
0143 ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
0144 nand@0,0 {
0145 compatible = "ti,omap2-nand";
0146 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
0147 interrupt-parent = <&gpmc>;
0148 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
0149 <1 IRQ_TYPE_NONE>; /* termcount */
0150 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
0151 ti,nand-ecc-opt = "bch8";
0152 ti,elm-id = <&elm>;
0153 nand-bus-width = <8>;
0154 gpmc,device-width = <1>;
0155 gpmc,sync-clk-ps = <0>;
0156 gpmc,cs-on-ns = <0>;
0157 gpmc,cs-rd-off-ns = <44>;
0158 gpmc,cs-wr-off-ns = <44>;
0159 gpmc,adv-on-ns = <6>;
0160 gpmc,adv-rd-off-ns = <34>;
0161 gpmc,adv-wr-off-ns = <44>;
0162 gpmc,we-on-ns = <0>;
0163 gpmc,we-off-ns = <40>;
0164 gpmc,oe-on-ns = <0>;
0165 gpmc,oe-off-ns = <54>;
0166 gpmc,access-ns = <64>;
0167 gpmc,rd-cycle-ns = <82>;
0168 gpmc,wr-cycle-ns = <82>;
0169 gpmc,bus-turnaround-ns = <0>;
0170 gpmc,cycle2cycle-delay-ns = <0>;
0171 gpmc,clk-activation-ns = <0>;
0172 gpmc,wr-access-ns = <40>;
0173 gpmc,wr-data-mux-bus-ns = <0>;
0174 };
0175 };
