0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
0004 */
0005
0006 /*
0007 * VScom OnRISC
0008 * http://www.vscom.de
0009 */
0010
0011 #include "am33xx.dtsi"
0012 #include <dt-bindings/pwm/pwm.h>
0013 #include <dt-bindings/interrupt-controller/irq.h>
0014
0015 / {
0016 compatible = "vscom,onrisc", "ti,am33xx";
0017
0018 cpus {
0019 cpu@0 {
0020 cpu0-supply = <&vdd1_reg>;
0021 };
0022 };
0023
0024 memory@80000000 {
0025 device_type = "memory";
0026 reg = <0x80000000 0x10000000>; /* 256 MB */
0027 };
0028
0029 vbat: fixedregulator0 {
0030 compatible = "regulator-fixed";
0031 regulator-name = "vbat";
0032 regulator-min-microvolt = <5000000>;
0033 regulator-max-microvolt = <5000000>;
0034 regulator-boot-on;
0035 };
0036
0037 wl12xx_vmmc: fixedregulator2 {
0038 pinctrl-names = "default";
0039 pinctrl-0 = <&wl12xx_gpio>;
0040 compatible = "regulator-fixed";
0041 regulator-name = "vwl1271";
0042 regulator-min-microvolt = <3300000>;
0043 regulator-max-microvolt = <3300000>;
0044 gpio = <&gpio3 8 0>;
0045 startup-delay-us = <70000>;
0046 enable-active-high;
0047 };
0048 };
0049
0050 &am33xx_pinmux {
0051 mmc2_pins: pinmux_mmc2_pins {
0052 pinctrl-single,pins = <
0053 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */
0054 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */
0055 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */
0056 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */
0057 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */
0058 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */
0059 AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLUP, MUX_MODE7) /* emu0.gpio3[7] */
0060 >;
0061 };
0062
0063 wl12xx_gpio: pinmux_wl12xx_gpio {
0064 pinctrl-single,pins = <
0065 AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */
0066 >;
0067 };
0068
0069 tps65910_pins: pinmux_tps65910_pins {
0070 pinctrl-single,pins = <
0071 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ben1.gpio1[28] */
0072 >;
0073 };
0074
0075 i2c1_pins: pinmux_i2c1_pins {
0076 pinctrl-single,pins = <
0077 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */
0078 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */
0079 >;
0080 };
0081
0082 uart0_pins: pinmux_uart0_pins {
0083 pinctrl-single,pins = <
0084 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
0085 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
0086 >;
0087 };
0088
0089 cpsw_default: cpsw_default {
0090 pinctrl-single,pins = <
0091 /* Slave 1 */
0092 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
0093 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_tx_en.rmii1_txen */
0094 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
0095 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
0096 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
0097 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
0098 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
0099
0100
0101 /* Slave 2 */
0102 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
0103 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
0104 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
0105 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
0106 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
0107 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
0108 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
0109 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
0110 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
0111 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
0112 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
0113 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
0114 >;
0115 };
0116
0117 cpsw_sleep: cpsw_sleep {
0118 pinctrl-single,pins = <
0119 /* Slave 1 reset value */
0120 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
0121 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
0122 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
0123 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
0124 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
0125 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
0126 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
0127
0128 /* Slave 2 reset value*/
0129 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
0130 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)
0131 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)
0132 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)
0133 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
0134 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
0135 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)
0136 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)
0137 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)
0138 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)
0139 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
0140 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
0141 >;
0142 };
0143
0144 davinci_mdio_default: davinci_mdio_default {
0145 pinctrl-single,pins = <
0146 /* MDIO */
0147 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data.mdio_data */
0148 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk.mdio_clk */
0149 >;
0150 };
0151
0152 davinci_mdio_sleep: davinci_mdio_sleep {
0153 pinctrl-single,pins = <
0154 /* MDIO reset value */
0155 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
0156 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
0157 >;
0158 };
0159
0160 nandflash_pins_s0: nandflash_pins_s0 {
0161 pinctrl-single,pins = <
0162 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0163 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0164 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0165 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0166 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0167 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0168 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0169 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0170 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0171 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
0172 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0173 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0174 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0175 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen.gpmc_wen */
0176 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
0177 >;
0178 };
0179 };
0180
0181 &elm {
0182 status = "okay";
0183 };
0184
0185 &gpmc {
0186 pinctrl-names = "default";
0187 pinctrl-0 = <&nandflash_pins_s0>;
0188 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
0189 status = "okay";
0190
0191 nand@0,0 {
0192 compatible = "ti,omap2-nand";
0193 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
0194 interrupt-parent = <&gpmc>;
0195 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
0196 <1 IRQ_TYPE_NONE>; /* termcount */
0197 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
0198 nand-bus-width = <8>;
0199 ti,nand-ecc-opt = "bch8";
0200 ti,nand-xfer-type = "polled";
0201
0202 gpmc,device-nand = "true";
0203 gpmc,device-width = <1>;
0204 gpmc,sync-clk-ps = <0>;
0205 gpmc,cs-on-ns = <0>;
0206 gpmc,cs-rd-off-ns = <44>;
0207 gpmc,cs-wr-off-ns = <44>;
0208 gpmc,adv-on-ns = <6>;
0209 gpmc,adv-rd-off-ns = <34>;
0210 gpmc,adv-wr-off-ns = <44>;
0211 gpmc,we-on-ns = <0>;
0212 gpmc,we-off-ns = <40>;
0213 gpmc,oe-on-ns = <0>;
0214 gpmc,oe-off-ns = <54>;
0215 gpmc,access-ns = <64>;
0216 gpmc,rd-cycle-ns = <82>;
0217 gpmc,wr-cycle-ns = <82>;
0218 gpmc,bus-turnaround-ns = <0>;
0219 gpmc,cycle2cycle-delay-ns = <0>;
0220 gpmc,clk-activation-ns = <0>;
0221 gpmc,wr-access-ns = <40>;
0222 gpmc,wr-data-mux-bus-ns = <0>;
0223
0224 #address-cells = <1>;
0225 #size-cells = <1>;
0226 ti,elm-id = <&elm>;
0227 };
0228 };
0229
0230 &uart0 {
0231 pinctrl-names = "default";
0232 pinctrl-0 = <&uart0_pins>;
0233
0234 status = "okay";
0235 };
0236
0237 &i2c1 {
0238 pinctrl-names = "default";
0239 pinctrl-0 = <&i2c1_pins>;
0240
0241 status = "okay";
0242 clock-frequency = <400000>;
0243
0244 tps: tps@2d {
0245 reg = <0x2d>;
0246 gpio-controller;
0247 #gpio-cells = <2>;
0248 interrupt-parent = <&gpio1>;
0249 interrupts = <28 IRQ_TYPE_EDGE_RISING>;
0250 pinctrl-names = "default";
0251 pinctrl-0 = <&tps65910_pins>;
0252 };
0253
0254 at24@50 {
0255 compatible = "atmel,24c02";
0256 pagesize = <8>;
0257 reg = <0x50>;
0258 };
0259 };
0260
0261 #include "tps65910.dtsi"
0262
0263 &tps {
0264 vcc1-supply = <&vbat>;
0265 vcc2-supply = <&vbat>;
0266 vcc3-supply = <&vbat>;
0267 vcc4-supply = <&vbat>;
0268 vcc5-supply = <&vbat>;
0269 vcc6-supply = <&vbat>;
0270 vcc7-supply = <&vbat>;
0271 vccio-supply = <&vbat>;
0272
0273 ti,en-ck32k-xtal = <1>;
0274
0275 regulators {
0276 vrtc_reg: regulator@0 {
0277 regulator-always-on;
0278 };
0279
0280 vio_reg: regulator@1 {
0281 regulator-always-on;
0282 };
0283
0284 vdd1_reg: regulator@2 {
0285 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
0286 regulator-name = "vdd_mpu";
0287 regulator-min-microvolt = <912500>;
0288 regulator-max-microvolt = <1351500>;
0289 regulator-boot-on;
0290 regulator-always-on;
0291 };
0292
0293 vdd2_reg: regulator@3 {
0294 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
0295 regulator-name = "vdd_core";
0296 regulator-min-microvolt = <912500>;
0297 regulator-max-microvolt = <1150000>;
0298 regulator-boot-on;
0299 regulator-always-on;
0300 };
0301
0302 vdd3_reg: regulator@4 {
0303 regulator-always-on;
0304 };
0305
0306 vdig1_reg: regulator@5 {
0307 regulator-always-on;
0308 };
0309
0310 vdig2_reg: regulator@6 {
0311 regulator-always-on;
0312 };
0313
0314 vpll_reg: regulator@7 {
0315 regulator-always-on;
0316 };
0317
0318 vdac_reg: regulator@8 {
0319 regulator-always-on;
0320 };
0321
0322 vaux1_reg: regulator@9 {
0323 regulator-always-on;
0324 };
0325
0326 vaux2_reg: regulator@10 {
0327 regulator-always-on;
0328 };
0329
0330 vaux33_reg: regulator@11 {
0331 regulator-always-on;
0332 };
0333
0334 vmmc_reg: regulator@12 {
0335 regulator-min-microvolt = <1800000>;
0336 regulator-max-microvolt = <3300000>;
0337 regulator-always-on;
0338 };
0339 };
0340 };
0341
0342 &mac_sw {
0343 pinctrl-names = "default", "sleep";
0344 pinctrl-0 = <&cpsw_default>;
0345 pinctrl-1 = <&cpsw_sleep>;
0346
0347 status = "okay";
0348 };
0349
0350 &davinci_mdio_sw {
0351 status = "okay";
0352 pinctrl-names = "default", "sleep";
0353 pinctrl-0 = <&davinci_mdio_default>;
0354 pinctrl-1 = <&davinci_mdio_sleep>;
0355
0356 phy1: ethernet-phy@1 {
0357 reg = <7>;
0358 eee-broken-100tx;
0359 eee-broken-1000t;
0360 };
0361 };
0362
0363 &mmc1 {
0364 vmmc-supply = <&vmmc_reg>;
0365 status = "okay";
0366 };
0367
0368 &mmc2 {
0369 status = "okay";
0370 vmmc-supply = <&wl12xx_vmmc>;
0371 non-removable;
0372 bus-width = <4>;
0373 cap-power-off-card;
0374 pinctrl-names = "default";
0375 pinctrl-0 = <&mmc2_pins>;
0376
0377 #address-cells = <1>;
0378 #size-cells = <0>;
0379 wlcore: wlcore@2 {
0380 compatible = "ti,wl1835";
0381 reg = <2>;
0382 interrupt-parent = <&gpio3>;
0383 interrupts = <7 IRQ_TYPE_EDGE_RISING>;
0384 };
0385 };
0386
0387 &sham {
0388 status = "okay";
0389 };
0390
0391 &aes {
0392 status = "okay";
0393 };
0394
0395 &gpio0_target {
0396 ti,no-reset-on-init;
0397 };
0398
0399 &gpio3_target {
0400 ti,no-reset-on-init;
0401 };
