0001 /*
0002 * Copyright 2015 Annapurna Labs Ltd.
0003 *
0004 * This program is free software; you can redistribute it and/or modify it
0005 * under the terms and conditions of the GNU General Public License,
0006 * version 2, as published by the Free Software Foundation.
0007 *
0008 * Alternatively, redistribution and use in source and binary forms, with or
0009 * without modification, are permitted provided that the following conditions
0010 * are met:
0011 *
0012 * * Redistributions of source code must retain the above copyright notice,
0013 * this list of conditions and the following disclaimer.
0014 *
0015 * * Redistributions in binary form must reproduce the above copyright
0016 * notice, this list of conditions and the following disclaimer in
0017 * the documentation and/or other materials provided with the
0018 * distribution.
0019 *
0020 * This program is distributed in the hope it will be useful, but WITHOUT
0021 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0022 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
0023 * more details.
0024 *
0025 */
0026
0027 #include <dt-bindings/interrupt-controller/arm-gic.h>
0028
0029 / {
0030 #address-cells = <2>;
0031 #size-cells = <2>;
0032 /* SOC compatibility */
0033 compatible = "al,alpine";
0034
0035 memory {
0036 device_type = "memory";
0037 reg = <0 0 0 0>;
0038 };
0039
0040 /* CPU Configuration */
0041 cpus {
0042 #address-cells = <1>;
0043 #size-cells = <0>;
0044 enable-method = "al,alpine-smp";
0045
0046 cpu@0 {
0047 compatible = "arm,cortex-a15";
0048 device_type = "cpu";
0049 reg = <0>;
0050 clock-frequency = <1700000000>;
0051 };
0052
0053 cpu@1 {
0054 compatible = "arm,cortex-a15";
0055 device_type = "cpu";
0056 reg = <1>;
0057 clock-frequency = <1700000000>;
0058 };
0059
0060 cpu@2 {
0061 compatible = "arm,cortex-a15";
0062 device_type = "cpu";
0063 reg = <2>;
0064 clock-frequency = <1700000000>;
0065 };
0066
0067 cpu@3 {
0068 compatible = "arm,cortex-a15";
0069 device_type = "cpu";
0070 reg = <3>;
0071 clock-frequency = <1700000000>;
0072 };
0073 };
0074
0075 soc {
0076 #address-cells = <2>;
0077 #size-cells = <2>;
0078 compatible = "simple-bus";
0079 interrupt-parent = <&gic>;
0080 ranges;
0081
0082 arch-timer {
0083 compatible = "arm,cortex-a15-timer",
0084 "arm,armv7-timer";
0085 interrupts =
0086 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0087 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0088 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0089 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0090 clock-frequency = <50000000>;
0091 };
0092
0093 /* Interrupt Controller */
0094 gic: interrupt-controller@fb001000 {
0095 compatible = "arm,cortex-a15-gic";
0096 #interrupt-cells = <3>;
0097 #size-cells = <0>;
0098 #address-cells = <0>;
0099 interrupt-controller;
0100 reg = <0x0 0xfb001000 0x0 0x1000>,
0101 <0x0 0xfb002000 0x0 0x2000>,
0102 <0x0 0xfb004000 0x0 0x2000>,
0103 <0x0 0xfb006000 0x0 0x2000>;
0104 interrupts =
0105 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0106 };
0107
0108 /* CPU Resume registers */
0109 cpu-resume@fbff5ec0 {
0110 compatible = "al,alpine-cpu-resume";
0111 reg = <0x0 0xfbff5ec0 0x0 0x30>;
0112 };
0113
0114 /* North Bridge Service Registers */
0115 sysfabric-service@fb070000 {
0116 compatible = "al,alpine-sysfabric-service", "syscon";
0117 reg = <0x0 0xfb070000 0x0 0x10000>;
0118 };
0119
0120 /* Performance Monitor Unit */
0121 pmu {
0122 compatible = "arm,cortex-a15-pmu";
0123 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
0124 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
0125 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0126 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0127 };
0128
0129 uart0: uart@fd883000 {
0130 compatible = "ns16550a";
0131 reg = <0x0 0xfd883000 0x0 0x1000>;
0132 clock-frequency = <375000000>;
0133 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0134 reg-shift = <2>;
0135 reg-io-width = <4>;
0136 };
0137
0138 uart1: uart@fd884000 {
0139 compatible = "ns16550a";
0140 reg = <0x0 0xfd884000 0x0 0x1000>;
0141 clock-frequency = <375000000>;
0142 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0143 reg-shift = <2>;
0144 reg-io-width = <4>;
0145 };
0146
0147 /* Internal PCIe Controller */
0148 pcie@fbc00000 {
0149 compatible = "pci-host-ecam-generic";
0150 device_type = "pci";
0151 #size-cells = <2>;
0152 #address-cells = <3>;
0153 #interrupt-cells = <1>;
0154 reg = <0x0 0xfbc00000 0x0 0x100000>;
0155 interrupt-map-mask = <0xf800 0 0 7>;
0156 /* Add legacy interrupts for SATA devices only */
0157 interrupt-map = <0x4000 0 0 1 &gic 0 43 4>,
0158 <0x4800 0 0 1 &gic 0 44 4>;
0159
0160 /* 32 bit non prefetchable memory space */
0161 ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
0162
0163 bus-range = <0x00 0x00>;
0164 msi-parent = <&msix>;
0165 };
0166
0167 msix: msix@fbe00000 {
0168 compatible = "al,alpine-msix";
0169 reg = <0x0 0xfbe00000 0x0 0x100000>;
0170 interrupt-controller;
0171 msi-controller;
0172 al,msi-base-spi = <96>;
0173 al,msi-num-spis = <64>;
0174 };
0175 };
0176 };
