boot/compressed/head-sa1100.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * linux/arch/arm/boot/compressed/head-sa1100.S
0004  *
0005  * Copyright (C) 1999 Nicolas Pitre <nico@fluxnic.net>
0006  *
0007  * SA1100 specific tweaks.  This is merged into head.S by the linker.
0008  *
0009  */
0010
0011 #include <linux/linkage.h>
0012 #include <asm/mach-types.h>
0013
0014         .section        ".start", "ax"
0015         .arch   armv4
0016
0017 __SA1100_start:
0018
0019         @ Preserve r8/r7 i.e. kernel entry values
0020 #ifdef CONFIG_SA1100_COLLIE
0021         mov r7, #MACH_TYPE_COLLIE
0022 #endif
0023 #ifdef CONFIG_SA1100_SIMPAD
0024         @ UNTIL we've something like an open bootldr
0025         mov r7, #MACH_TYPE_SIMPAD   @should be 87
0026 #endif
0027         mrc p15, 0, r0, c1, c0, 0   @ read control reg
0028         ands    r0, r0, #0x0d
0029         beq 99f
0030
0031         @ Data cache might be active.
0032         @ Be sure to flush kernel binary out of the cache,
0033         @ whatever state it is, before it is turned off.
0034         @ This is done by fetching through currently executed
0035         @ memory to be sure we hit the same cache.
0036         bic r2, pc, #0x1f
0037         add r3, r2, #0x4000     @ 16 kb is quite enough...
0038 1:      ldr r0, [r2], #32
0039         teq r2, r3
0040         bne 1b
0041         mcr p15, 0, r0, c7, c10, 4  @ drain WB
0042         mcr p15, 0, r0, c7, c7, 0   @ flush I & D caches
0043
0044         @ disabling MMU and caches
0045         mrc p15, 0, r0, c1, c0, 0   @ read control reg
0046         bic r0, r0, #0x0d       @ clear WB, DC, MMU
0047         bic r0, r0, #0x1000     @ clear Icache
0048         mcr p15, 0, r0, c1, c0, 0
0049 99: