arc/plat-axs10x/axs10x.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AXS101/AXS103 Software Development Platform
0004  *
0005  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
0006  */
0007
0008 #include <linux/of_fdt.h>
0009 #include <linux/of_platform.h>
0010 #include <linux/libfdt.h>
0011
0012 #include <asm/asm-offsets.h>
0013 #include <asm/io.h>
0014 #include <asm/mach_desc.h>
0015 #include <soc/arc/mcip.h>
0016
0017 #define AXS_MB_CGU      0xE0010000
0018 #define AXS_MB_CREG     0xE0011000
0019
0020 #define CREG_MB_IRQ_MUX     (AXS_MB_CREG + 0x214)
0021 #define CREG_MB_SW_RESET    (AXS_MB_CREG + 0x220)
0022 #define CREG_MB_VER     (AXS_MB_CREG + 0x230)
0023 #define CREG_MB_CONFIG      (AXS_MB_CREG + 0x234)
0024
0025 #define AXC001_CREG     0xF0001000
0026 #define AXC001_GPIO_INTC    0xF0003000
0027
0028 static void __init axs10x_enable_gpio_intc_wire(void)
0029 {
0030     /*
0031      * Peripherals on CPU Card and Mother Board are wired to cpu intc via
0032      * intermediate DW APB GPIO blocks (mainly for debouncing)
0033      *
0034      *         ---------------------
0035      *        |  snps,arc700-intc |
0036      *        ---------------------
0037      *          | #7          | #15
0038      * -------------------   -------------------
0039      * | snps,dw-apb-gpio |  | snps,dw-apb-gpio |
0040      * -------------------   -------------------
0041      *        | #12                     |
0042      *        |                 [ Debug UART on cpu card ]
0043      *        |
0044      * ------------------------
0045      * | snps,dw-apb-intc (MB)|
0046      * ------------------------
0047      *  |      |       |      |
0048      * [eth] [uart]        [... other perip on Main Board]
0049      *
0050      * Current implementation of "irq-dw-apb-ictl" driver doesn't work well
0051      * with stacked INTCs. In particular problem happens if its master INTC
0052      * not yet instantiated. See discussion here -
0053      * https://lore.kernel.org/lkml/54F6FE2C.7020309@synopsys.com
0054      *
0055      * So setup the first gpio block as a passive pass thru and hide it from
0056      * DT hardware topology - connect MB intc directly to cpu intc
0057      * The GPIO "wire" needs to be init nevertheless (here)
0058      *
0059      * One side adv is that peripheral interrupt handling avoids one nested
0060      * intc ISR hop
0061      */
0062 #define GPIO_INTEN      (AXC001_GPIO_INTC + 0x30)
0063 #define GPIO_INTMASK        (AXC001_GPIO_INTC + 0x34)
0064 #define GPIO_INTTYPE_LEVEL  (AXC001_GPIO_INTC + 0x38)
0065 #define GPIO_INT_POLARITY   (AXC001_GPIO_INTC + 0x3c)
0066 #define MB_TO_GPIO_IRQ      12
0067
0068     iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK);
0069     iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL);
0070     iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY);
0071     iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);
0072 }
0073
0074 static void __init axs10x_print_board_ver(unsigned int creg, const char *str)
0075 {
0076     union ver {
0077         struct {
0078 #ifdef CONFIG_CPU_BIG_ENDIAN
0079             unsigned int pad:11, y:12, m:4, d:5;
0080 #else
0081             unsigned int d:5, m:4, y:12, pad:11;
0082 #endif
0083         };
0084         unsigned int val;
0085     } board;
0086
0087     board.val = ioread32((void __iomem *)creg);
0088     pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m,
0089         board.y);
0090 }
0091
0092 static void __init axs10x_early_init(void)
0093 {
0094     int mb_rev;
0095     char mb[32];
0096
0097     /* Determine motherboard version */
0098     if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28))
0099         mb_rev = 3; /* HT-3 (rev3.0) */
0100     else
0101         mb_rev = 2; /* HT-2 (rev2.0) */
0102
0103     axs10x_enable_gpio_intc_wire();
0104
0105     scnprintf(mb, 32, "MainBoard v%d", mb_rev);
0106     axs10x_print_board_ver(CREG_MB_VER, mb);
0107 }
0108
0109 #ifdef CONFIG_AXS101
0110
0111 #define CREG_CPU_ADDR_770   (AXC001_CREG + 0x20)
0112 #define CREG_CPU_ADDR_TUNN  (AXC001_CREG + 0x60)
0113 #define CREG_CPU_ADDR_770_UPD   (AXC001_CREG + 0x34)
0114 #define CREG_CPU_ADDR_TUNN_UPD  (AXC001_CREG + 0x74)
0115
0116 #define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114)
0117 #define CREG_CPU_GPIO_UART_MUX  (AXC001_CREG + 0x120)
0118
0119 /*
0120  * Set up System Memory Map for ARC cpu / peripherals controllers
0121  *
0122  * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
0123  * of which maps to a corresponding 256MB aperture in Target slave memory map.
0124  *
0125  * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
0126  * (0x0000_0000) of DDR Port 0 (slave #1)
0127  *
0128  * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
0129  * which has master/slaves on both ends.
0130  * e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14
0131  * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
0132  * MB AXI Tunnel Master, which also has a mem map setup
0133  *
0134  * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
0135  * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
0136  */
0137 struct aperture {
0138     unsigned int slave_sel:4, slave_off:4, pad:24;
0139 };
0140
0141 /* CPU Card target slaves */
0142 #define AXC001_SLV_NONE         0
0143 #define AXC001_SLV_DDR_PORT0        1
0144 #define AXC001_SLV_SRAM         2
0145 #define AXC001_SLV_AXI_TUNNEL       3
0146 #define AXC001_SLV_AXI2APB      6
0147 #define AXC001_SLV_DDR_PORT1        7
0148
0149 /* MB AXI Target slaves */
0150 #define AXS_MB_SLV_NONE         0
0151 #define AXS_MB_SLV_AXI_TUNNEL_CPU   1
0152 #define AXS_MB_SLV_AXI_TUNNEL_HAPS  2
0153 #define AXS_MB_SLV_SRAM         3
0154 #define AXS_MB_SLV_CONTROL      4
0155
0156 /* MB AXI masters */
0157 #define AXS_MB_MST_TUNNEL_CPU       0
0158 #define AXS_MB_MST_USB_OHCI     10
0159
0160 /*
0161  * memmap for ARC core on CPU Card
0162  */
0163 static const struct aperture axc001_memmap[16] = {
0164     {AXC001_SLV_AXI_TUNNEL,     0x0},
0165     {AXC001_SLV_AXI_TUNNEL,     0x1},
0166     {AXC001_SLV_SRAM,       0x0}, /* 0x2000_0000: Local SRAM */
0167     {AXC001_SLV_NONE,       0x0},
0168     {AXC001_SLV_NONE,       0x0},
0169     {AXC001_SLV_NONE,       0x0},
0170     {AXC001_SLV_NONE,       0x0},
0171     {AXC001_SLV_NONE,       0x0},
0172     {AXC001_SLV_DDR_PORT0,      0x0}, /* 0x8000_0000: DDR   0..256M */
0173     {AXC001_SLV_DDR_PORT0,      0x1}, /* 0x9000_0000: DDR 256..512M */
0174     {AXC001_SLV_DDR_PORT0,      0x2},
0175     {AXC001_SLV_DDR_PORT0,      0x3},
0176     {AXC001_SLV_NONE,       0x0},
0177     {AXC001_SLV_AXI_TUNNEL,     0xD},
0178     {AXC001_SLV_AXI_TUNNEL,     0xE}, /* MB: CREG, CGU... */
0179     {AXC001_SLV_AXI2APB,        0x0}, /* CPU Card local CREG, CGU... */
0180 };
0181
0182 /*
0183  * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
0184  * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
0185  */
0186 static const struct aperture axc001_axi_tunnel_memmap[16] = {
0187     {AXC001_SLV_AXI_TUNNEL,     0x0},
0188     {AXC001_SLV_AXI_TUNNEL,     0x1},
0189     {AXC001_SLV_SRAM,       0x0},
0190     {AXC001_SLV_NONE,       0x0},
0191     {AXC001_SLV_NONE,       0x0},
0192     {AXC001_SLV_NONE,       0x0},
0193     {AXC001_SLV_NONE,       0x0},
0194     {AXC001_SLV_NONE,       0x0},
0195     {AXC001_SLV_DDR_PORT1,      0x0},
0196     {AXC001_SLV_DDR_PORT1,      0x1},
0197     {AXC001_SLV_DDR_PORT1,      0x2},
0198     {AXC001_SLV_DDR_PORT1,      0x3},
0199     {AXC001_SLV_NONE,       0x0},
0200     {AXC001_SLV_AXI_TUNNEL,     0xD},
0201     {AXC001_SLV_AXI_TUNNEL,     0xE},
0202     {AXC001_SLV_AXI2APB,        0x0},
0203 };
0204
0205 /*
0206  * memmap for MB AXI Masters
0207  * Same mem map for all perip controllers as well as MB AXI Tunnel Master
0208  */
0209 static const struct aperture axs_mb_memmap[16] = {
0210     {AXS_MB_SLV_SRAM,       0x0},
0211     {AXS_MB_SLV_SRAM,       0x0},
0212     {AXS_MB_SLV_NONE,       0x0},
0213     {AXS_MB_SLV_NONE,       0x0},
0214     {AXS_MB_SLV_NONE,       0x0},
0215     {AXS_MB_SLV_NONE,       0x0},
0216     {AXS_MB_SLV_NONE,       0x0},
0217     {AXS_MB_SLV_NONE,       0x0},
0218     {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x8},   /* DDR on CPU Card */
0219     {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x9},   /* DDR on CPU Card */
0220     {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xA},
0221     {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xB},
0222     {AXS_MB_SLV_NONE,       0x0},
0223     {AXS_MB_SLV_AXI_TUNNEL_HAPS,    0xD},
0224     {AXS_MB_SLV_CONTROL,        0x0},   /* MB Local CREG, CGU... */
0225     {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xF},
0226 };
0227
0228 static noinline void __init
0229 axs101_set_memmap(void __iomem *base, const struct aperture map[16])
0230 {
0231     unsigned int slave_select, slave_offset;
0232     int i;
0233
0234     slave_select = slave_offset = 0;
0235     for (i = 0; i < 8; i++) {
0236         slave_select |= map[i].slave_sel << (i << 2);
0237         slave_offset |= map[i].slave_off << (i << 2);
0238     }
0239
0240     iowrite32(slave_select, base + 0x0);    /* SLV0 */
0241     iowrite32(slave_offset, base + 0x8);    /* OFFSET0 */
0242
0243     slave_select = slave_offset = 0;
0244     for (i = 0; i < 8; i++) {
0245         slave_select |= map[i+8].slave_sel << (i << 2);
0246         slave_offset |= map[i+8].slave_off << (i << 2);
0247     }
0248
0249     iowrite32(slave_select, base + 0x4);    /* SLV1 */
0250     iowrite32(slave_offset, base + 0xC);    /* OFFSET1 */
0251 }
0252
0253 static void __init axs101_early_init(void)
0254 {
0255     int i;
0256
0257     /* ARC 770D memory view */
0258     axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap);
0259     iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD);
0260
0261     /* AXI tunnel memory map (incoming traffic from MB into CPU Card */
0262     axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN,
0263                   axc001_axi_tunnel_memmap);
0264     iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD);
0265
0266     /* MB peripherals memory map */
0267     for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++)
0268         axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4),
0269                       axs_mb_memmap);
0270
0271     iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */
0272
0273     /* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */
0274     iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
0275
0276     /* Set up the MB interrupt system: mux interrupts to GPIO7) */
0277     iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
0278
0279     /* reset ethernet and ULPI interfaces */
0280     iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET);
0281
0282     /* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */
0283     iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX);
0284
0285     axs10x_early_init();
0286 }
0287
0288 #endif  /* CONFIG_AXS101 */
0289
0290 #ifdef CONFIG_AXS103
0291
0292 #define AXC003_CREG 0xF0001000
0293 #define AXC003_MST_AXI_TUNNEL   0
0294 #define AXC003_MST_HS38     1
0295
0296 #define CREG_CPU_AXI_M0_IRQ_MUX (AXC003_CREG + 0x440)
0297 #define CREG_CPU_GPIO_UART_MUX  (AXC003_CREG + 0x480)
0298 #define CREG_CPU_TUN_IO_CTRL    (AXC003_CREG + 0x494)
0299
0300
0301 static void __init axs103_early_init(void)
0302 {
0303 #ifdef CONFIG_ARC_MCIP
0304     /*
0305      * AXS103 configurations for SMP/QUAD configurations share device tree
0306      * which defaults to 100 MHz. However recent failures of Quad config
0307      * revealed P&R timing violations so clamp it down to safe 50 MHz
0308      * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
0309      * of fudging the freq in DT
0310      */
0311 #define AXS103_QUAD_CORE_CPU_FREQ_HZ    50000000
0312
0313     unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
0314     if (num_cores > 2) {
0315         u32 freq;
0316         int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
0317         const struct fdt_property *prop;
0318
0319         prop = fdt_get_property(initial_boot_params, off,
0320                     "assigned-clock-rates", NULL);
0321         freq = be32_to_cpu(*(u32 *)(prop->data));
0322
0323         /* Patching .dtb in-place with new core clock value */
0324         if (freq != AXS103_QUAD_CORE_CPU_FREQ_HZ) {
0325             freq = cpu_to_be32(AXS103_QUAD_CORE_CPU_FREQ_HZ);
0326             fdt_setprop_inplace(initial_boot_params, off,
0327                         "assigned-clock-rates", &freq, sizeof(freq));
0328         }
0329     }
0330 #endif
0331
0332     /* Memory maps already config in pre-bootloader */
0333
0334     /* set GPIO mux to UART */
0335     iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
0336
0337     iowrite32((0x00100000U | 0x000C0000U | 0x00003322U),
0338           (void __iomem *) CREG_CPU_TUN_IO_CTRL);
0339
0340     /* Set up the AXS_MB interrupt system.*/
0341     iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX
0342                      + (AXC003_MST_HS38 << 2)));
0343
0344     /* connect ICTL - Main Board with GPIO line */
0345     iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
0346
0347     axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card");
0348
0349     axs10x_early_init();
0350 }
0351 #endif
0352
0353 #ifdef CONFIG_AXS101
0354
0355 static const char *axs101_compat[] __initconst = {
0356     "snps,axs101",
0357     NULL,
0358 };
0359
0360 MACHINE_START(AXS101, "axs101")
0361     .dt_compat  = axs101_compat,
0362     .init_early = axs101_early_init,
0363 MACHINE_END
0364
0365 #endif  /* CONFIG_AXS101 */
0366
0367 #ifdef CONFIG_AXS103
0368
0369 static const char *axs103_compat[] __initconst = {
0370     "snps,axs103",
0371     NULL,
0372 };
0373
0374 MACHINE_START(AXS103, "axs103")
0375     .dt_compat  = axs103_compat,
0376     .init_early = axs103_early_init,
0377 MACHINE_END
0378
0379 /*
0380  * For the VDK OS-kit, to get the offset to pid and command fields
0381  */
0382 char coware_swa_pid_offset[TASK_PID];
0383 char coware_swa_comm_offset[TASK_COMM];
0384
0385 #endif  /* CONFIG_AXS103 */