arc/mm/tlb.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * TLB Management (flush/create/diagnostics) for MMUv3 and MMUv4
0004  *
0005  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
0006  *
0007  */
0008
0009 #include <linux/module.h>
0010 #include <linux/bug.h>
0011 #include <linux/mm_types.h>
0012
0013 #include <asm/arcregs.h>
0014 #include <asm/setup.h>
0015 #include <asm/mmu_context.h>
0016 #include <asm/mmu.h>
0017
0018 /* A copy of the ASID from the PID reg is kept in asid_cache */
0019 DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
0020
0021 static int __read_mostly pae_exists;
0022
0023 /*
0024  * Utility Routine to erase a J-TLB entry
0025  * Caller needs to setup Index Reg (manually or via getIndex)
0026  */
0027 static inline void __tlb_entry_erase(void)
0028 {
0029     write_aux_reg(ARC_REG_TLBPD1, 0);
0030
0031     if (is_pae40_enabled())
0032         write_aux_reg(ARC_REG_TLBPD1HI, 0);
0033
0034     write_aux_reg(ARC_REG_TLBPD0, 0);
0035     write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
0036 }
0037
0038 static void utlb_invalidate(void)
0039 {
0040     write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
0041 }
0042
0043 #ifdef CONFIG_ARC_MMU_V3
0044
0045 static inline unsigned int tlb_entry_lkup(unsigned long vaddr_n_asid)
0046 {
0047     unsigned int idx;
0048
0049     write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);
0050
0051     write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
0052     idx = read_aux_reg(ARC_REG_TLBINDEX);
0053
0054     return idx;
0055 }
0056
0057 static void tlb_entry_erase(unsigned int vaddr_n_asid)
0058 {
0059     unsigned int idx;
0060
0061     /* Locate the TLB entry for this vaddr + ASID */
0062     idx = tlb_entry_lkup(vaddr_n_asid);
0063
0064     /* No error means entry found, zero it out */
0065     if (likely(!(idx & TLB_LKUP_ERR))) {
0066         __tlb_entry_erase();
0067     } else {
0068         /* Duplicate entry error */
0069         WARN(idx == TLB_DUP_ERR, "Probe returned Dup PD for %x\n",
0070                        vaddr_n_asid);
0071     }
0072 }
0073
0074 static void tlb_entry_insert(unsigned int pd0, phys_addr_t pd1)
0075 {
0076     unsigned int idx;
0077
0078     /*
0079      * First verify if entry for this vaddr+ASID already exists
0080      * This also sets up PD0 (vaddr, ASID..) for final commit
0081      */
0082     idx = tlb_entry_lkup(pd0);
0083
0084     /*
0085      * If Not already present get a free slot from MMU.
0086      * Otherwise, Probe would have located the entry and set INDEX Reg
0087      * with existing location. This will cause Write CMD to over-write
0088      * existing entry with new PD0 and PD1
0089      */
0090     if (likely(idx & TLB_LKUP_ERR))
0091         write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex);
0092
0093     /* setup the other half of TLB entry (pfn, rwx..) */
0094     write_aux_reg(ARC_REG_TLBPD1, pd1);
0095
0096     /*
0097      * Commit the Entry to MMU
0098      * It doesn't sound safe to use the TLBWriteNI cmd here
0099      * which doesn't flush uTLBs. I'd rather be safe than sorry.
0100      */
0101     write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
0102 }
0103
0104 #else   /* MMUv4 */
0105
0106 static void tlb_entry_erase(unsigned int vaddr_n_asid)
0107 {
0108     write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT);
0109     write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry);
0110 }
0111
0112 static void tlb_entry_insert(unsigned int pd0, phys_addr_t pd1)
0113 {
0114     write_aux_reg(ARC_REG_TLBPD0, pd0);
0115
0116     if (!is_pae40_enabled()) {
0117         write_aux_reg(ARC_REG_TLBPD1, pd1);
0118     } else {
0119         write_aux_reg(ARC_REG_TLBPD1, pd1 & 0xFFFFFFFF);
0120         write_aux_reg(ARC_REG_TLBPD1HI, (u64)pd1 >> 32);
0121     }
0122
0123     write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry);
0124 }
0125
0126 #endif
0127
0128 /*
0129  * Un-conditionally (without lookup) erase the entire MMU contents
0130  */
0131
0132 noinline void local_flush_tlb_all(void)
0133 {
0134     struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
0135     unsigned long flags;
0136     unsigned int entry;
0137     int num_tlb = mmu->sets * mmu->ways;
0138
0139     local_irq_save(flags);
0140
0141     /* Load PD0 and PD1 with template for a Blank Entry */
0142     write_aux_reg(ARC_REG_TLBPD1, 0);
0143
0144     if (is_pae40_enabled())
0145         write_aux_reg(ARC_REG_TLBPD1HI, 0);
0146
0147     write_aux_reg(ARC_REG_TLBPD0, 0);
0148
0149     for (entry = 0; entry < num_tlb; entry++) {
0150         /* write this entry to the TLB */
0151         write_aux_reg(ARC_REG_TLBINDEX, entry);
0152         write_aux_reg(ARC_REG_TLBCOMMAND, TLBWriteNI);
0153     }
0154
0155     if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) {
0156         const int stlb_idx = 0x800;
0157
0158         /* Blank sTLB entry */
0159         write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ);
0160
0161         for (entry = stlb_idx; entry < stlb_idx + 16; entry++) {
0162             write_aux_reg(ARC_REG_TLBINDEX, entry);
0163             write_aux_reg(ARC_REG_TLBCOMMAND, TLBWriteNI);
0164         }
0165     }
0166
0167     utlb_invalidate();
0168
0169     local_irq_restore(flags);
0170 }
0171
0172 /*
0173  * Flush the entire MM for userland. The fastest way is to move to Next ASID
0174  */
0175 noinline void local_flush_tlb_mm(struct mm_struct *mm)
0176 {
0177     /*
0178      * Small optimisation courtesy IA64
0179      * flush_mm called during fork,exit,munmap etc, multiple times as well.
0180      * Only for fork( ) do we need to move parent to a new MMU ctxt,
0181      * all other cases are NOPs, hence this check.
0182      */
0183     if (atomic_read(&mm->mm_users) == 0)
0184         return;
0185
0186     /*
0187      * - Move to a new ASID, but only if the mm is still wired in
0188      *   (Android Binder ended up calling this for vma->mm != tsk->mm,
0189      *    causing h/w - s/w ASID to get out of sync)
0190      * - Also get_new_mmu_context() new implementation allocates a new
0191      *   ASID only if it is not allocated already - so unallocate first
0192      */
0193     destroy_context(mm);
0194     if (current->mm == mm)
0195         get_new_mmu_context(mm);
0196 }
0197
0198 /*
0199  * Flush a Range of TLB entries for userland.
0200  * @start is inclusive, while @end is exclusive
0201  * Difference between this and Kernel Range Flush is
0202  *  -Here the fastest way (if range is too large) is to move to next ASID
0203  *      without doing any explicit Shootdown
0204  *  -In case of kernel Flush, entry has to be shot down explicitly
0205  */
0206 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
0207                unsigned long end)
0208 {
0209     const unsigned int cpu = smp_processor_id();
0210     unsigned long flags;
0211
0212     /* If range @start to @end is more than 32 TLB entries deep,
0213      * its better to move to a new ASID rather than searching for
0214      * individual entries and then shooting them down
0215      *
0216      * The calc above is rough, doesn't account for unaligned parts,
0217      * since this is heuristics based anyways
0218      */
0219     if (unlikely((end - start) >= PAGE_SIZE * 32)) {
0220         local_flush_tlb_mm(vma->vm_mm);
0221         return;
0222     }
0223
0224     /*
0225      * @start moved to page start: this alone suffices for checking
0226      * loop end condition below, w/o need for aligning @end to end
0227      * e.g. 2000 to 4001 will anyhow loop twice
0228      */
0229     start &= PAGE_MASK;
0230
0231     local_irq_save(flags);
0232
0233     if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
0234         while (start < end) {
0235             tlb_entry_erase(start | hw_pid(vma->vm_mm, cpu));
0236             start += PAGE_SIZE;
0237         }
0238     }
0239
0240     local_irq_restore(flags);
0241 }
0242
0243 /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
0244  *  @start, @end interpreted as kvaddr
0245  * Interestingly, shared TLB entries can also be flushed using just
0246  * @start,@end alone (interpreted as user vaddr), although technically SASID
0247  * is also needed. However our smart TLbProbe lookup takes care of that.
0248  */
0249 void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
0250 {
0251     unsigned long flags;
0252
0253     /* exactly same as above, except for TLB entry not taking ASID */
0254
0255     if (unlikely((end - start) >= PAGE_SIZE * 32)) {
0256         local_flush_tlb_all();
0257         return;
0258     }
0259
0260     start &= PAGE_MASK;
0261
0262     local_irq_save(flags);
0263     while (start < end) {
0264         tlb_entry_erase(start);
0265         start += PAGE_SIZE;
0266     }
0267
0268     local_irq_restore(flags);
0269 }
0270
0271 /*
0272  * Delete TLB entry in MMU for a given page (??? address)
0273  * NOTE One TLB entry contains translation for single PAGE
0274  */
0275
0276 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
0277 {
0278     const unsigned int cpu = smp_processor_id();
0279     unsigned long flags;
0280
0281     /* Note that it is critical that interrupts are DISABLED between
0282      * checking the ASID and using it flush the TLB entry
0283      */
0284     local_irq_save(flags);
0285
0286     if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
0287         tlb_entry_erase((page & PAGE_MASK) | hw_pid(vma->vm_mm, cpu));
0288     }
0289
0290     local_irq_restore(flags);
0291 }
0292
0293 #ifdef CONFIG_SMP
0294
0295 struct tlb_args {
0296     struct vm_area_struct *ta_vma;
0297     unsigned long ta_start;
0298     unsigned long ta_end;
0299 };
0300
0301 static inline void ipi_flush_tlb_page(void *arg)
0302 {
0303     struct tlb_args *ta = arg;
0304
0305     local_flush_tlb_page(ta->ta_vma, ta->ta_start);
0306 }
0307
0308 static inline void ipi_flush_tlb_range(void *arg)
0309 {
0310     struct tlb_args *ta = arg;
0311
0312     local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
0313 }
0314
0315 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
0316 static inline void ipi_flush_pmd_tlb_range(void *arg)
0317 {
0318     struct tlb_args *ta = arg;
0319
0320     local_flush_pmd_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
0321 }
0322 #endif
0323
0324 static inline void ipi_flush_tlb_kernel_range(void *arg)
0325 {
0326     struct tlb_args *ta = (struct tlb_args *)arg;
0327
0328     local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
0329 }
0330
0331 void flush_tlb_all(void)
0332 {
0333     on_each_cpu((smp_call_func_t)local_flush_tlb_all, NULL, 1);
0334 }
0335
0336 void flush_tlb_mm(struct mm_struct *mm)
0337 {
0338     on_each_cpu_mask(mm_cpumask(mm), (smp_call_func_t)local_flush_tlb_mm,
0339              mm, 1);
0340 }
0341
0342 void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
0343 {
0344     struct tlb_args ta = {
0345         .ta_vma = vma,
0346         .ta_start = uaddr
0347     };
0348
0349     on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page, &ta, 1);
0350 }
0351
0352 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
0353              unsigned long end)
0354 {
0355     struct tlb_args ta = {
0356         .ta_vma = vma,
0357         .ta_start = start,
0358         .ta_end = end
0359     };
0360
0361     on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_range, &ta, 1);
0362 }
0363
0364 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
0365 void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
0366              unsigned long end)
0367 {
0368     struct tlb_args ta = {
0369         .ta_vma = vma,
0370         .ta_start = start,
0371         .ta_end = end
0372     };
0373
0374     on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_pmd_tlb_range, &ta, 1);
0375 }
0376 #endif
0377
0378 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
0379 {
0380     struct tlb_args ta = {
0381         .ta_start = start,
0382         .ta_end = end
0383     };
0384
0385     on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
0386 }
0387 #endif
0388
0389 /*
0390  * Routine to create a TLB entry
0391  */
0392 void create_tlb(struct vm_area_struct *vma, unsigned long vaddr, pte_t *ptep)
0393 {
0394     unsigned long flags;
0395     unsigned int asid_or_sasid, rwx;
0396     unsigned long pd0;
0397     phys_addr_t pd1;
0398
0399     /*
0400      * create_tlb() assumes that current->mm == vma->mm, since
0401      * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)
0402      * -completes the lazy write to SASID reg (again valid for curr tsk)
0403      *
0404      * Removing the assumption involves
0405      * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
0406      * -More importantly it makes this handler inconsistent with fast-path
0407      *  TLB Refill handler which always deals with "current"
0408      *
0409      * Lets see the use cases when current->mm != vma->mm and we land here
0410      *  1. execve->copy_strings()->__get_user_pages->handle_mm_fault
0411      *     Here VM wants to pre-install a TLB entry for user stack while
0412      *     current->mm still points to pre-execve mm (hence the condition).
0413      *     However the stack vaddr is soon relocated (randomization) and
0414      *     move_page_tables() tries to undo that TLB entry.
0415      *     Thus not creating TLB entry is not any worse.
0416      *
0417      *  2. ptrace(POKETEXT) causes a CoW - debugger(current) inserting a
0418      *     breakpoint in debugged task. Not creating a TLB now is not
0419      *     performance critical.
0420      *
0421      * Both the cases above are not good enough for code churn.
0422      */
0423     if (current->active_mm != vma->vm_mm)
0424         return;
0425
0426     local_irq_save(flags);
0427
0428     vaddr &= PAGE_MASK;
0429
0430     /* update this PTE credentials */
0431     pte_val(*ptep) |= (_PAGE_PRESENT | _PAGE_ACCESSED);
0432
0433     /* Create HW TLB(PD0,PD1) from PTE  */
0434
0435     /* ASID for this task */
0436     asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;
0437
0438     pd0 = vaddr | asid_or_sasid | (pte_val(*ptep) & PTE_BITS_IN_PD0);
0439
0440     /*
0441      * ARC MMU provides fully orthogonal access bits for K/U mode,
0442      * however Linux only saves 1 set to save PTE real-estate
0443      * Here we convert 3 PTE bits into 6 MMU bits:
0444      * -Kernel only entries have Kr Kw Kx 0 0 0
0445      * -User entries have mirrored K and U bits
0446      */
0447     rwx = pte_val(*ptep) & PTE_BITS_RWX;
0448
0449     if (pte_val(*ptep) & _PAGE_GLOBAL)
0450         rwx <<= 3;      /* r w x => Kr Kw Kx 0 0 0 */
0451     else
0452         rwx |= (rwx << 3);  /* r w x => Kr Kw Kx Ur Uw Ux */
0453
0454     pd1 = rwx | (pte_val(*ptep) & PTE_BITS_NON_RWX_IN_PD1);
0455
0456     tlb_entry_insert(pd0, pd1);
0457
0458     local_irq_restore(flags);
0459 }
0460
0461 /*
0462  * Called at the end of pagefault, for a userspace mapped page
0463  *  -pre-install the corresponding TLB entry into MMU
0464  *  -Finalize the delayed D-cache flush of kernel mapping of page due to
0465  *      flush_dcache_page(), copy_user_page()
0466  *
0467  * Note that flush (when done) involves both WBACK - so physical page is
0468  * in sync as well as INV - so any non-congruent aliases don't remain
0469  */
0470 void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
0471               pte_t *ptep)
0472 {
0473     unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
0474     phys_addr_t paddr = pte_val(*ptep) & PAGE_MASK_PHYS;
0475     struct page *page = pfn_to_page(pte_pfn(*ptep));
0476
0477     create_tlb(vma, vaddr, ptep);
0478
0479     if (page == ZERO_PAGE(0)) {
0480         return;
0481     }
0482
0483     /*
0484      * Exec page : Independent of aliasing/page-color considerations,
0485      *         since icache doesn't snoop dcache on ARC, any dirty
0486      *         K-mapping of a code page needs to be wback+inv so that
0487      *         icache fetch by userspace sees code correctly.
0488      * !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it
0489      *         so userspace sees the right data.
0490      *  (Avoids the flush for Non-exec + congruent mapping case)
0491      */
0492     if ((vma->vm_flags & VM_EXEC) ||
0493          addr_not_cache_congruent(paddr, vaddr)) {
0494
0495         int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
0496         if (dirty) {
0497             /* wback + inv dcache lines (K-mapping) */
0498             __flush_dcache_page(paddr, paddr);
0499
0500             /* invalidate any existing icache lines (U-mapping) */
0501             if (vma->vm_flags & VM_EXEC)
0502                 __inv_icache_page(paddr, vaddr);
0503         }
0504     }
0505 }
0506
0507 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
0508
0509 /*
0510  * MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP
0511  * support.
0512  *
0513  * Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a
0514  * new bit "SZ" in TLB page descriptor to distinguish between them.
0515  * Super Page size is configurable in hardware (4K to 16M), but fixed once
0516  * RTL builds.
0517  *
0518  * The exact THP size a Linux configuration will support is a function of:
0519  *  - MMU page size (typical 8K, RTL fixed)
0520  *  - software page walker address split between PGD:PTE:PFN (typical
0521  *    11:8:13, but can be changed with 1 line)
0522  * So for above default, THP size supported is 8K * (2^8) = 2M
0523  *
0524  * Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime
0525  * reduces to 1 level (as PTE is folded into PGD and canonically referred
0526  * to as PMD).
0527  * Thus THP PMD accessors are implemented in terms of PTE (just like sparc)
0528  */
0529
0530 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
0531                  pmd_t *pmd)
0532 {
0533     pte_t pte = __pte(pmd_val(*pmd));
0534     update_mmu_cache(vma, addr, &pte);
0535 }
0536
0537 void local_flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
0538                    unsigned long end)
0539 {
0540     unsigned int cpu;
0541     unsigned long flags;
0542
0543     local_irq_save(flags);
0544
0545     cpu = smp_processor_id();
0546
0547     if (likely(asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID)) {
0548         unsigned int asid = hw_pid(vma->vm_mm, cpu);
0549
0550         /* No need to loop here: this will always be for 1 Huge Page */
0551         tlb_entry_erase(start | _PAGE_HW_SZ | asid);
0552     }
0553
0554     local_irq_restore(flags);
0555 }
0556
0557 #endif
0558
0559 /* Read the Cache Build Configuration Registers, Decode them and save into
0560  * the cpuinfo structure for later use.
0561  * No Validation is done here, simply read/convert the BCRs
0562  */
0563 void read_decode_mmu_bcr(void)
0564 {
0565     struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
0566     unsigned int tmp;
0567     struct bcr_mmu_3 {
0568 #ifdef CONFIG_CPU_BIG_ENDIAN
0569     unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,
0570              u_itlb:4, u_dtlb:4;
0571 #else
0572     unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4,
0573              ways:4, ver:8;
0574 #endif
0575     } *mmu3;
0576
0577     struct bcr_mmu_4 {
0578 #ifdef CONFIG_CPU_BIG_ENDIAN
0579     unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
0580              n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
0581 #else
0582     /*           DTLB      ITLB      JES        JE         JA      */
0583     unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
0584              pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
0585 #endif
0586     } *mmu4;
0587
0588     tmp = read_aux_reg(ARC_REG_MMU_BCR);
0589     mmu->ver = (tmp >> 24);
0590
0591     if (is_isa_arcompact() && mmu->ver == 3) {
0592         mmu3 = (struct bcr_mmu_3 *)&tmp;
0593         mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);
0594         mmu->sets = 1 << mmu3->sets;
0595         mmu->ways = 1 << mmu3->ways;
0596         mmu->u_dtlb = mmu3->u_dtlb;
0597         mmu->u_itlb = mmu3->u_itlb;
0598         mmu->sasid = mmu3->sasid;
0599     } else {
0600         mmu4 = (struct bcr_mmu_4 *)&tmp;
0601         mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);
0602         mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11);
0603         mmu->sets = 64 << mmu4->n_entry;
0604         mmu->ways = mmu4->n_ways * 2;
0605         mmu->u_dtlb = mmu4->u_dtlb * 4;
0606         mmu->u_itlb = mmu4->u_itlb * 4;
0607         mmu->sasid = mmu4->sasid;
0608         pae_exists = mmu->pae = mmu4->pae;
0609     }
0610 }
0611
0612 char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
0613 {
0614     int n = 0;
0615     struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
0616     char super_pg[64] = "";
0617
0618     if (p_mmu->s_pg_sz_m)
0619         scnprintf(super_pg, 64, "%dM Super Page %s",
0620               p_mmu->s_pg_sz_m,
0621               IS_USED_CFG(CONFIG_TRANSPARENT_HUGEPAGE));
0622
0623     n += scnprintf(buf + n, len - n,
0624               "MMU [v%x]\t: %dk PAGE, %s, swalk %d lvl, JTLB %d (%dx%d), uDTLB %d, uITLB %d%s%s\n",
0625                p_mmu->ver, p_mmu->pg_sz_k, super_pg,  CONFIG_PGTABLE_LEVELS,
0626                p_mmu->sets * p_mmu->ways, p_mmu->sets, p_mmu->ways,
0627                p_mmu->u_dtlb, p_mmu->u_itlb,
0628                IS_AVAIL2(p_mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40));
0629
0630     return buf;
0631 }
0632
0633 int pae40_exist_but_not_enab(void)
0634 {
0635     return pae_exists && !is_pae40_enabled();
0636 }
0637
0638 void arc_mmu_init(void)
0639 {
0640     struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
0641     char str[256];
0642     int compat = 0;
0643
0644     pr_info("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
0645
0646     /*
0647      * Can't be done in processor.h due to header include dependencies
0648      */
0649     BUILD_BUG_ON(!IS_ALIGNED((CONFIG_ARC_KVADDR_SIZE << 20), PMD_SIZE));
0650
0651     /*
0652      * stack top size sanity check,
0653      * Can't be done in processor.h due to header include dependencies
0654      */
0655     BUILD_BUG_ON(!IS_ALIGNED(STACK_TOP, PMD_SIZE));
0656
0657     /*
0658      * Ensure that MMU features assumed by kernel exist in hardware.
0659      *  - For older ARC700 cpus, only v3 supported
0660      *  - For HS cpus, v4 was baseline and v5 is backwards compatible
0661      *    (will run older software).
0662      */
0663     if (is_isa_arcompact() && mmu->ver == 3)
0664         compat = 1;
0665     else if (is_isa_arcv2() && mmu->ver >= 4)
0666         compat = 1;
0667
0668     if (!compat)
0669         panic("MMU ver %d doesn't match kernel built for\n", mmu->ver);
0670
0671     if (mmu->pg_sz_k != TO_KB(PAGE_SIZE))
0672         panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
0673
0674     if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) &&
0675         mmu->s_pg_sz_m != TO_MB(HPAGE_PMD_SIZE))
0676         panic("MMU Super pg size != Linux HPAGE_PMD_SIZE (%luM)\n",
0677               (unsigned long)TO_MB(HPAGE_PMD_SIZE));
0678
0679     if (IS_ENABLED(CONFIG_ARC_HAS_PAE40) && !mmu->pae)
0680         panic("Hardware doesn't support PAE40\n");
0681
0682     /* Enable the MMU with ASID 0 */
0683     mmu_setup_asid(NULL, 0);
0684
0685     /* cache the pgd pointer in MMU SCRATCH reg (ARCv2 only) */
0686     mmu_setup_pgd(NULL, swapper_pg_dir);
0687
0688     if (pae40_exist_but_not_enab())
0689         write_aux_reg(ARC_REG_TLBPD1HI, 0);
0690 }
0691
0692 /*
0693  * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
0694  * The mapping is Column-first.
0695  *      ---------------------   -----------
0696  *      |way0|way1|way2|way3|   |way0|way1|
0697  *      ---------------------   -----------
0698  * [set0]   |  0 |  1 |  2 |  3 |   |  0 |  1 |
0699  * [set1]   |  4 |  5 |  6 |  7 |   |  2 |  3 |
0700  *      ~           ~   ~     ~
0701  * [set127] | 508| 509| 510| 511|   | 254| 255|
0702  *      ---------------------   -----------
0703  * For normal operations we don't(must not) care how above works since
0704  * MMU cmd getIndex(vaddr) abstracts that out.
0705  * However for walking WAYS of a SET, we need to know this
0706  */
0707 #define SET_WAY_TO_IDX(mmu, set, way)  ((set) * mmu->ways + (way))
0708
0709 /* Handling of Duplicate PD (TLB entry) in MMU.
0710  * -Could be due to buggy customer tapeouts or obscure kernel bugs
0711  * -MMU complaints not at the time of duplicate PD installation, but at the
0712  *      time of lookup matching multiple ways.
0713  * -Ideally these should never happen - but if they do - workaround by deleting
0714  *      the duplicate one.
0715  * -Knob to be verbose abt it.(TODO: hook them up to debugfs)
0716  */
0717 volatile int dup_pd_silent; /* Be silent abt it or complain (default) */
0718
0719 void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
0720               struct pt_regs *regs)
0721 {
0722     struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
0723     unsigned long flags;
0724     int set, n_ways = mmu->ways;
0725
0726     n_ways = min(n_ways, 4);
0727     BUG_ON(mmu->ways > 4);
0728
0729     local_irq_save(flags);
0730
0731     /* loop thru all sets of TLB */
0732     for (set = 0; set < mmu->sets; set++) {
0733
0734         int is_valid, way;
0735         unsigned int pd0[4];
0736
0737         /* read out all the ways of current set */
0738         for (way = 0, is_valid = 0; way < n_ways; way++) {
0739             write_aux_reg(ARC_REG_TLBINDEX,
0740                       SET_WAY_TO_IDX(mmu, set, way));
0741             write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead);
0742             pd0[way] = read_aux_reg(ARC_REG_TLBPD0);
0743             is_valid |= pd0[way] & _PAGE_PRESENT;
0744             pd0[way] &= PAGE_MASK;
0745         }
0746
0747         /* If all the WAYS in SET are empty, skip to next SET */
0748         if (!is_valid)
0749             continue;
0750
0751         /* Scan the set for duplicate ways: needs a nested loop */
0752         for (way = 0; way < n_ways - 1; way++) {
0753
0754             int n;
0755
0756             if (!pd0[way])
0757                 continue;
0758
0759             for (n = way + 1; n < n_ways; n++) {
0760                 if (pd0[way] != pd0[n])
0761                     continue;
0762
0763                 if (!dup_pd_silent)
0764                     pr_info("Dup TLB PD0 %08x @ set %d ways %d,%d\n",
0765                         pd0[way], set, way, n);
0766
0767                 /*
0768                  * clear entry @way and not @n.
0769                  * This is critical to our optimised loop
0770                  */
0771                 pd0[way] = 0;
0772                 write_aux_reg(ARC_REG_TLBINDEX,
0773                         SET_WAY_TO_IDX(mmu, set, way));
0774                 __tlb_entry_erase();
0775             }
0776         }
0777     }
0778
0779     local_irq_restore(flags);
0780 }