arc/lib/memcmp.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
0004  */
0005
0006 #include <linux/linkage.h>
0007
0008 #ifdef __LITTLE_ENDIAN__
0009 #define WORD2 r2
0010 #define SHIFT r3
0011 #else /* BIG ENDIAN */
0012 #define WORD2 r3
0013 #define SHIFT r2
0014 #endif
0015
0016 ENTRY_CFI(memcmp)
0017     or  r12,r0,r1
0018     asl_s   r12,r12,30
0019     sub r3,r2,1
0020     brls    r2,r12,.Lbytewise
0021     ld  r4,[r0,0]
0022     ld  r5,[r1,0]
0023     lsr.f   lp_count,r3,3
0024 #ifdef CONFIG_ISA_ARCV2
0025     /* In ARCv2 a branch can't be the last instruction in a zero overhead
0026      * loop.
0027      * So we move the branch to the start of the loop, duplicate it
0028      * after the end, and set up r12 so that the branch isn't taken
0029      *  initially.
0030      */
0031     mov_s   r12,WORD2
0032     lpne    .Loop_end
0033     brne    WORD2,r12,.Lodd
0034     ld  WORD2,[r0,4]
0035 #else
0036     lpne    .Loop_end
0037     ld_s    WORD2,[r0,4]
0038 #endif
0039     ld_s    r12,[r1,4]
0040     brne    r4,r5,.Leven
0041     ld.a    r4,[r0,8]
0042     ld.a    r5,[r1,8]
0043 #ifdef CONFIG_ISA_ARCV2
0044 .Loop_end:
0045     brne    WORD2,r12,.Lodd
0046 #else
0047     brne    WORD2,r12,.Lodd
0048 .Loop_end:
0049 #endif
0050     asl_s   SHIFT,SHIFT,3
0051     bhs_s   .Last_cmp
0052     brne    r4,r5,.Leven
0053     ld  r4,[r0,4]
0054     ld  r5,[r1,4]
0055 #ifdef __LITTLE_ENDIAN__
0056     nop_s
0057     ; one more load latency cycle
0058 .Last_cmp:
0059     xor r0,r4,r5
0060     bset    r0,r0,SHIFT
0061     sub_s   r1,r0,1
0062     bic_s   r1,r1,r0
0063     norm    r1,r1
0064     b.d .Leven_cmp
0065     and r1,r1,24
0066 .Leven:
0067     xor r0,r4,r5
0068     sub_s   r1,r0,1
0069     bic_s   r1,r1,r0
0070     norm    r1,r1
0071     ; slow track insn
0072     and r1,r1,24
0073 .Leven_cmp:
0074     asl r2,r4,r1
0075     asl r12,r5,r1
0076     lsr_s   r2,r2,1
0077     lsr_s   r12,r12,1
0078     j_s.d   [blink]
0079     sub r0,r2,r12
0080     .balign 4
0081 .Lodd:
0082     xor r0,WORD2,r12
0083     sub_s   r1,r0,1
0084     bic_s   r1,r1,r0
0085     norm    r1,r1
0086     ; slow track insn
0087     and r1,r1,24
0088     asl_s   r2,r2,r1
0089     asl_s   r12,r12,r1
0090     lsr_s   r2,r2,1
0091     lsr_s   r12,r12,1
0092     j_s.d   [blink]
0093     sub r0,r2,r12
0094 #else /* BIG ENDIAN */
0095 .Last_cmp:
0096     neg_s   SHIFT,SHIFT
0097     lsr r4,r4,SHIFT
0098     lsr r5,r5,SHIFT
0099     ; slow track insn
0100 .Leven:
0101     sub.f   r0,r4,r5
0102     mov.ne  r0,1
0103     j_s.d   [blink]
0104     bset.cs r0,r0,31
0105 .Lodd:
0106     cmp_s   WORD2,r12
0107     mov_s   r0,1
0108     j_s.d   [blink]
0109     bset.cs r0,r0,31
0110 #endif /* ENDIAN */
0111     .balign 4
0112 .Lbytewise:
0113     breq    r2,0,.Lnil
0114     ldb r4,[r0,0]
0115     ldb r5,[r1,0]
0116     lsr.f   lp_count,r3
0117 #ifdef CONFIG_ISA_ARCV2
0118     mov r12,r3
0119     lpne    .Lbyte_end
0120     brne    r3,r12,.Lbyte_odd
0121 #else
0122     lpne    .Lbyte_end
0123 #endif
0124     ldb_s   r3,[r0,1]
0125     ldb r12,[r1,1]
0126     brne    r4,r5,.Lbyte_even
0127     ldb.a   r4,[r0,2]
0128     ldb.a   r5,[r1,2]
0129 #ifdef CONFIG_ISA_ARCV2
0130 .Lbyte_end:
0131     brne    r3,r12,.Lbyte_odd
0132 #else
0133     brne    r3,r12,.Lbyte_odd
0134 .Lbyte_end:
0135 #endif
0136     bcc .Lbyte_even
0137     brne    r4,r5,.Lbyte_even
0138     ldb_s   r3,[r0,1]
0139     ldb_s   r12,[r1,1]
0140 .Lbyte_odd:
0141     j_s.d   [blink]
0142     sub r0,r3,r12
0143 .Lbyte_even:
0144     j_s.d   [blink]
0145     sub r0,r4,r5
0146 .Lnil:
0147     j_s.d   [blink]
0148     mov r0,0
0149 END_CFI(memcmp)