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0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Linux performance counter support for ARC CPUs.
0004 // This code is inspired by the perf support of various other architectures.
0005 //
0006 // Copyright (C) 2013-2018 Synopsys, Inc. (www.synopsys.com)
0007 
0008 #include <linux/errno.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/perf_event.h>
0013 #include <linux/platform_device.h>
0014 #include <asm/arcregs.h>
0015 #include <asm/stacktrace.h>
0016 
0017 /* HW holds 8 symbols + one for null terminator */
0018 #define ARCPMU_EVENT_NAME_LEN   9
0019 
0020 /*
0021  * Some ARC pct quirks:
0022  *
0023  * PERF_COUNT_HW_STALLED_CYCLES_BACKEND
0024  * PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
0025  *  The ARC 700 can either measure stalls per pipeline stage, or all stalls
0026  *  combined; for now we assign all stalls to STALLED_CYCLES_BACKEND
0027  *  and all pipeline flushes (e.g. caused by mispredicts, etc.) to
0028  *  STALLED_CYCLES_FRONTEND.
0029  *
0030  *  We could start multiple performance counters and combine everything
0031  *  afterwards, but that makes it complicated.
0032  *
0033  *  Note that I$ cache misses aren't counted by either of the two!
0034  */
0035 
0036 /*
0037  * ARC PCT has hardware conditions with fixed "names" but variable "indexes"
0038  * (based on a specific RTL build)
0039  * Below is the static map between perf generic/arc specific event_id and
0040  * h/w condition names.
0041  * At the time of probe, we loop thru each index and find it's name to
0042  * complete the mapping of perf event_id to h/w index as latter is needed
0043  * to program the counter really
0044  */
0045 static const char * const arc_pmu_ev_hw_map[] = {
0046     /* count cycles */
0047     [PERF_COUNT_HW_CPU_CYCLES] = "crun",
0048     [PERF_COUNT_HW_REF_CPU_CYCLES] = "crun",
0049     [PERF_COUNT_HW_BUS_CYCLES] = "crun",
0050 
0051     [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush",
0052     [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall",
0053 
0054     /* counts condition */
0055     [PERF_COUNT_HW_INSTRUCTIONS] = "iall",
0056     /* All jump instructions that are taken */
0057     [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmptak",
0058 #ifdef CONFIG_ISA_ARCV2
0059     [PERF_COUNT_HW_BRANCH_MISSES] = "bpmp",
0060 #else
0061     [PERF_COUNT_ARC_BPOK]         = "bpok",   /* NP-NT, PT-T, PNT-NT */
0062     [PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */
0063 #endif
0064     [PERF_COUNT_ARC_LDC] = "imemrdc",   /* Instr: mem read cached */
0065     [PERF_COUNT_ARC_STC] = "imemwrc",   /* Instr: mem write cached */
0066 
0067     [PERF_COUNT_ARC_DCLM] = "dclm",     /* D-cache Load Miss */
0068     [PERF_COUNT_ARC_DCSM] = "dcsm",     /* D-cache Store Miss */
0069     [PERF_COUNT_ARC_ICM] = "icm",       /* I-cache Miss */
0070     [PERF_COUNT_ARC_EDTLB] = "edtlb",   /* D-TLB Miss */
0071     [PERF_COUNT_ARC_EITLB] = "eitlb",   /* I-TLB Miss */
0072 
0073     [PERF_COUNT_HW_CACHE_REFERENCES] = "imemrdc",   /* Instr: mem read cached */
0074     [PERF_COUNT_HW_CACHE_MISSES] = "dclm",      /* D-cache Load Miss */
0075 };
0076 
0077 #define C(_x)           PERF_COUNT_HW_CACHE_##_x
0078 #define CACHE_OP_UNSUPPORTED    0xffff
0079 
0080 static const unsigned int arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
0081     [C(L1D)] = {
0082         [C(OP_READ)] = {
0083             [C(RESULT_ACCESS)]  = PERF_COUNT_ARC_LDC,
0084             [C(RESULT_MISS)]    = PERF_COUNT_ARC_DCLM,
0085         },
0086         [C(OP_WRITE)] = {
0087             [C(RESULT_ACCESS)]  = PERF_COUNT_ARC_STC,
0088             [C(RESULT_MISS)]    = PERF_COUNT_ARC_DCSM,
0089         },
0090         [C(OP_PREFETCH)] = {
0091             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0092             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0093         },
0094     },
0095     [C(L1I)] = {
0096         [C(OP_READ)] = {
0097             [C(RESULT_ACCESS)]  = PERF_COUNT_HW_INSTRUCTIONS,
0098             [C(RESULT_MISS)]    = PERF_COUNT_ARC_ICM,
0099         },
0100         [C(OP_WRITE)] = {
0101             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0102             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0103         },
0104         [C(OP_PREFETCH)] = {
0105             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0106             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0107         },
0108     },
0109     [C(LL)] = {
0110         [C(OP_READ)] = {
0111             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0112             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0113         },
0114         [C(OP_WRITE)] = {
0115             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0116             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0117         },
0118         [C(OP_PREFETCH)] = {
0119             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0120             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0121         },
0122     },
0123     [C(DTLB)] = {
0124         [C(OP_READ)] = {
0125             [C(RESULT_ACCESS)]  = PERF_COUNT_ARC_LDC,
0126             [C(RESULT_MISS)]    = PERF_COUNT_ARC_EDTLB,
0127         },
0128             /* DTLB LD/ST Miss not segregated by h/w*/
0129         [C(OP_WRITE)] = {
0130             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0131             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0132         },
0133         [C(OP_PREFETCH)] = {
0134             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0135             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0136         },
0137     },
0138     [C(ITLB)] = {
0139         [C(OP_READ)] = {
0140             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0141             [C(RESULT_MISS)]    = PERF_COUNT_ARC_EITLB,
0142         },
0143         [C(OP_WRITE)] = {
0144             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0145             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0146         },
0147         [C(OP_PREFETCH)] = {
0148             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0149             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0150         },
0151     },
0152     [C(BPU)] = {
0153         [C(OP_READ)] = {
0154             [C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
0155             [C(RESULT_MISS)]    = PERF_COUNT_HW_BRANCH_MISSES,
0156         },
0157         [C(OP_WRITE)] = {
0158             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0159             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0160         },
0161         [C(OP_PREFETCH)] = {
0162             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0163             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0164         },
0165     },
0166     [C(NODE)] = {
0167         [C(OP_READ)] = {
0168             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0169             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0170         },
0171         [C(OP_WRITE)] = {
0172             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0173             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0174         },
0175         [C(OP_PREFETCH)] = {
0176             [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
0177             [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
0178         },
0179     },
0180 };
0181 
0182 enum arc_pmu_attr_groups {
0183     ARCPMU_ATTR_GR_EVENTS,
0184     ARCPMU_ATTR_GR_FORMATS,
0185     ARCPMU_NR_ATTR_GR
0186 };
0187 
0188 struct arc_pmu_raw_event_entry {
0189     char name[ARCPMU_EVENT_NAME_LEN];
0190 };
0191 
0192 struct arc_pmu {
0193     struct pmu  pmu;
0194     unsigned int    irq;
0195     int     n_counters;
0196     int     n_events;
0197     u64     max_period;
0198     int     ev_hw_idx[PERF_COUNT_ARC_HW_MAX];
0199 
0200     struct arc_pmu_raw_event_entry  *raw_entry;
0201     struct attribute        **attrs;
0202     struct perf_pmu_events_attr *attr;
0203     const struct attribute_group    *attr_groups[ARCPMU_NR_ATTR_GR + 1];
0204 };
0205 
0206 struct arc_pmu_cpu {
0207     /*
0208      * A 1 bit for an index indicates that the counter is being used for
0209      * an event. A 0 means that the counter can be used.
0210      */
0211     unsigned long   used_mask[BITS_TO_LONGS(ARC_PERF_MAX_COUNTERS)];
0212 
0213     /*
0214      * The events that are active on the PMU for the given index.
0215      */
0216     struct perf_event *act_counter[ARC_PERF_MAX_COUNTERS];
0217 };
0218 
0219 struct arc_callchain_trace {
0220     int depth;
0221     void *perf_stuff;
0222 };
0223 
0224 static int callchain_trace(unsigned int addr, void *data)
0225 {
0226     struct arc_callchain_trace *ctrl = data;
0227     struct perf_callchain_entry_ctx *entry = ctrl->perf_stuff;
0228 
0229     perf_callchain_store(entry, addr);
0230 
0231     if (ctrl->depth++ < 3)
0232         return 0;
0233 
0234     return -1;
0235 }
0236 
0237 void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,
0238                struct pt_regs *regs)
0239 {
0240     struct arc_callchain_trace ctrl = {
0241         .depth = 0,
0242         .perf_stuff = entry,
0243     };
0244 
0245     arc_unwind_core(NULL, regs, callchain_trace, &ctrl);
0246 }
0247 
0248 void perf_callchain_user(struct perf_callchain_entry_ctx *entry,
0249              struct pt_regs *regs)
0250 {
0251     /*
0252      * User stack can't be unwound trivially with kernel dwarf unwinder
0253      * So for now just record the user PC
0254      */
0255     perf_callchain_store(entry, instruction_pointer(regs));
0256 }
0257 
0258 static struct arc_pmu *arc_pmu;
0259 static DEFINE_PER_CPU(struct arc_pmu_cpu, arc_pmu_cpu);
0260 
0261 /* read counter #idx; note that counter# != event# on ARC! */
0262 static u64 arc_pmu_read_counter(int idx)
0263 {
0264     u32 tmp;
0265     u64 result;
0266 
0267     /*
0268      * ARC supports making 'snapshots' of the counters, so we don't
0269      * need to care about counters wrapping to 0 underneath our feet
0270      */
0271     write_aux_reg(ARC_REG_PCT_INDEX, idx);
0272     tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
0273     write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN);
0274     result = (u64) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32;
0275     result |= read_aux_reg(ARC_REG_PCT_SNAPL);
0276 
0277     return result;
0278 }
0279 
0280 static void arc_perf_event_update(struct perf_event *event,
0281                   struct hw_perf_event *hwc, int idx)
0282 {
0283     u64 prev_raw_count = local64_read(&hwc->prev_count);
0284     u64 new_raw_count = arc_pmu_read_counter(idx);
0285     s64 delta = new_raw_count - prev_raw_count;
0286 
0287     /*
0288      * We aren't afraid of hwc->prev_count changing beneath our feet
0289      * because there's no way for us to re-enter this function anytime.
0290      */
0291     local64_set(&hwc->prev_count, new_raw_count);
0292     local64_add(delta, &event->count);
0293     local64_sub(delta, &hwc->period_left);
0294 }
0295 
0296 static void arc_pmu_read(struct perf_event *event)
0297 {
0298     arc_perf_event_update(event, &event->hw, event->hw.idx);
0299 }
0300 
0301 static int arc_pmu_cache_event(u64 config)
0302 {
0303     unsigned int cache_type, cache_op, cache_result;
0304     int ret;
0305 
0306     cache_type  = (config >>  0) & 0xff;
0307     cache_op    = (config >>  8) & 0xff;
0308     cache_result    = (config >> 16) & 0xff;
0309     if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
0310         return -EINVAL;
0311     if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
0312         return -EINVAL;
0313     if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
0314         return -EINVAL;
0315 
0316     ret = arc_pmu_cache_map[cache_type][cache_op][cache_result];
0317 
0318     if (ret == CACHE_OP_UNSUPPORTED)
0319         return -ENOENT;
0320 
0321     pr_debug("init cache event: type/op/result %d/%d/%d with h/w %d \'%s\'\n",
0322          cache_type, cache_op, cache_result, ret,
0323          arc_pmu_ev_hw_map[ret]);
0324 
0325     return ret;
0326 }
0327 
0328 /* initializes hw_perf_event structure if event is supported */
0329 static int arc_pmu_event_init(struct perf_event *event)
0330 {
0331     struct hw_perf_event *hwc = &event->hw;
0332     int ret;
0333 
0334     if (!is_sampling_event(event)) {
0335         hwc->sample_period = arc_pmu->max_period;
0336         hwc->last_period = hwc->sample_period;
0337         local64_set(&hwc->period_left, hwc->sample_period);
0338     }
0339 
0340     hwc->config = 0;
0341 
0342     if (is_isa_arcv2()) {
0343         /* "exclude user" means "count only kernel" */
0344         if (event->attr.exclude_user)
0345             hwc->config |= ARC_REG_PCT_CONFIG_KERN;
0346 
0347         /* "exclude kernel" means "count only user" */
0348         if (event->attr.exclude_kernel)
0349             hwc->config |= ARC_REG_PCT_CONFIG_USER;
0350     }
0351 
0352     switch (event->attr.type) {
0353     case PERF_TYPE_HARDWARE:
0354         if (event->attr.config >= PERF_COUNT_HW_MAX)
0355             return -ENOENT;
0356         if (arc_pmu->ev_hw_idx[event->attr.config] < 0)
0357             return -ENOENT;
0358         hwc->config |= arc_pmu->ev_hw_idx[event->attr.config];
0359         pr_debug("init event %d with h/w %08x \'%s\'\n",
0360              (int)event->attr.config, (int)hwc->config,
0361              arc_pmu_ev_hw_map[event->attr.config]);
0362         return 0;
0363 
0364     case PERF_TYPE_HW_CACHE:
0365         ret = arc_pmu_cache_event(event->attr.config);
0366         if (ret < 0)
0367             return ret;
0368         hwc->config |= arc_pmu->ev_hw_idx[ret];
0369         pr_debug("init cache event with h/w %08x \'%s\'\n",
0370              (int)hwc->config, arc_pmu_ev_hw_map[ret]);
0371         return 0;
0372 
0373     case PERF_TYPE_RAW:
0374         if (event->attr.config >= arc_pmu->n_events)
0375             return -ENOENT;
0376 
0377         hwc->config |= event->attr.config;
0378         pr_debug("init raw event with idx %lld \'%s\'\n",
0379              event->attr.config,
0380              arc_pmu->raw_entry[event->attr.config].name);
0381 
0382         return 0;
0383 
0384     default:
0385         return -ENOENT;
0386     }
0387 }
0388 
0389 /* starts all counters */
0390 static void arc_pmu_enable(struct pmu *pmu)
0391 {
0392     u32 tmp;
0393     tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
0394     write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1);
0395 }
0396 
0397 /* stops all counters */
0398 static void arc_pmu_disable(struct pmu *pmu)
0399 {
0400     u32 tmp;
0401     tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
0402     write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0);
0403 }
0404 
0405 static int arc_pmu_event_set_period(struct perf_event *event)
0406 {
0407     struct hw_perf_event *hwc = &event->hw;
0408     s64 left = local64_read(&hwc->period_left);
0409     s64 period = hwc->sample_period;
0410     int idx = hwc->idx;
0411     int overflow = 0;
0412     u64 value;
0413 
0414     if (unlikely(left <= -period)) {
0415         /* left underflowed by more than period. */
0416         left = period;
0417         local64_set(&hwc->period_left, left);
0418         hwc->last_period = period;
0419         overflow = 1;
0420     } else if (unlikely(left <= 0)) {
0421         /* left underflowed by less than period. */
0422         left += period;
0423         local64_set(&hwc->period_left, left);
0424         hwc->last_period = period;
0425         overflow = 1;
0426     }
0427 
0428     if (left > arc_pmu->max_period)
0429         left = arc_pmu->max_period;
0430 
0431     value = arc_pmu->max_period - left;
0432     local64_set(&hwc->prev_count, value);
0433 
0434     /* Select counter */
0435     write_aux_reg(ARC_REG_PCT_INDEX, idx);
0436 
0437     /* Write value */
0438     write_aux_reg(ARC_REG_PCT_COUNTL, lower_32_bits(value));
0439     write_aux_reg(ARC_REG_PCT_COUNTH, upper_32_bits(value));
0440 
0441     perf_event_update_userpage(event);
0442 
0443     return overflow;
0444 }
0445 
0446 /*
0447  * Assigns hardware counter to hardware condition.
0448  * Note that there is no separate start/stop mechanism;
0449  * stopping is achieved by assigning the 'never' condition
0450  */
0451 static void arc_pmu_start(struct perf_event *event, int flags)
0452 {
0453     struct hw_perf_event *hwc = &event->hw;
0454     int idx = hwc->idx;
0455 
0456     if (WARN_ON_ONCE(idx == -1))
0457         return;
0458 
0459     if (flags & PERF_EF_RELOAD)
0460         WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
0461 
0462     hwc->state = 0;
0463 
0464     arc_pmu_event_set_period(event);
0465 
0466     /* Enable interrupt for this counter */
0467     if (is_sampling_event(event))
0468         write_aux_reg(ARC_REG_PCT_INT_CTRL,
0469                   read_aux_reg(ARC_REG_PCT_INT_CTRL) | BIT(idx));
0470 
0471     /* enable ARC pmu here */
0472     write_aux_reg(ARC_REG_PCT_INDEX, idx);      /* counter # */
0473     write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config); /* condition */
0474 }
0475 
0476 static void arc_pmu_stop(struct perf_event *event, int flags)
0477 {
0478     struct hw_perf_event *hwc = &event->hw;
0479     int idx = hwc->idx;
0480 
0481     /* Disable interrupt for this counter */
0482     if (is_sampling_event(event)) {
0483         /*
0484          * Reset interrupt flag by writing of 1. This is required
0485          * to make sure pending interrupt was not left.
0486          */
0487         write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx));
0488         write_aux_reg(ARC_REG_PCT_INT_CTRL,
0489                   read_aux_reg(ARC_REG_PCT_INT_CTRL) & ~BIT(idx));
0490     }
0491 
0492     if (!(event->hw.state & PERF_HES_STOPPED)) {
0493         /* stop hw counter here */
0494         write_aux_reg(ARC_REG_PCT_INDEX, idx);
0495 
0496         /* condition code #0 is always "never" */
0497         write_aux_reg(ARC_REG_PCT_CONFIG, 0);
0498 
0499         event->hw.state |= PERF_HES_STOPPED;
0500     }
0501 
0502     if ((flags & PERF_EF_UPDATE) &&
0503         !(event->hw.state & PERF_HES_UPTODATE)) {
0504         arc_perf_event_update(event, &event->hw, idx);
0505         event->hw.state |= PERF_HES_UPTODATE;
0506     }
0507 }
0508 
0509 static void arc_pmu_del(struct perf_event *event, int flags)
0510 {
0511     struct arc_pmu_cpu *pmu_cpu = this_cpu_ptr(&arc_pmu_cpu);
0512 
0513     arc_pmu_stop(event, PERF_EF_UPDATE);
0514     __clear_bit(event->hw.idx, pmu_cpu->used_mask);
0515 
0516     pmu_cpu->act_counter[event->hw.idx] = 0;
0517 
0518     perf_event_update_userpage(event);
0519 }
0520 
0521 /* allocate hardware counter and optionally start counting */
0522 static int arc_pmu_add(struct perf_event *event, int flags)
0523 {
0524     struct arc_pmu_cpu *pmu_cpu = this_cpu_ptr(&arc_pmu_cpu);
0525     struct hw_perf_event *hwc = &event->hw;
0526     int idx;
0527 
0528     idx = ffz(pmu_cpu->used_mask[0]);
0529     if (idx == arc_pmu->n_counters)
0530         return -EAGAIN;
0531 
0532     __set_bit(idx, pmu_cpu->used_mask);
0533     hwc->idx = idx;
0534 
0535     write_aux_reg(ARC_REG_PCT_INDEX, idx);
0536 
0537     pmu_cpu->act_counter[idx] = event;
0538 
0539     if (is_sampling_event(event)) {
0540         /* Mimic full counter overflow as other arches do */
0541         write_aux_reg(ARC_REG_PCT_INT_CNTL,
0542                   lower_32_bits(arc_pmu->max_period));
0543         write_aux_reg(ARC_REG_PCT_INT_CNTH,
0544                   upper_32_bits(arc_pmu->max_period));
0545     }
0546 
0547     write_aux_reg(ARC_REG_PCT_CONFIG, 0);
0548     write_aux_reg(ARC_REG_PCT_COUNTL, 0);
0549     write_aux_reg(ARC_REG_PCT_COUNTH, 0);
0550     local64_set(&hwc->prev_count, 0);
0551 
0552     hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
0553     if (flags & PERF_EF_START)
0554         arc_pmu_start(event, PERF_EF_RELOAD);
0555 
0556     perf_event_update_userpage(event);
0557 
0558     return 0;
0559 }
0560 
0561 #ifdef CONFIG_ISA_ARCV2
0562 static irqreturn_t arc_pmu_intr(int irq, void *dev)
0563 {
0564     struct perf_sample_data data;
0565     struct arc_pmu_cpu *pmu_cpu = this_cpu_ptr(&arc_pmu_cpu);
0566     struct pt_regs *regs;
0567     unsigned int active_ints;
0568     int idx;
0569 
0570     arc_pmu_disable(&arc_pmu->pmu);
0571 
0572     active_ints = read_aux_reg(ARC_REG_PCT_INT_ACT);
0573     if (!active_ints)
0574         goto done;
0575 
0576     regs = get_irq_regs();
0577 
0578     do {
0579         struct perf_event *event;
0580         struct hw_perf_event *hwc;
0581 
0582         idx = __ffs(active_ints);
0583 
0584         /* Reset interrupt flag by writing of 1 */
0585         write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx));
0586 
0587         /*
0588          * On reset of "interrupt active" bit corresponding
0589          * "interrupt enable" bit gets automatically reset as well.
0590          * Now we need to re-enable interrupt for the counter.
0591          */
0592         write_aux_reg(ARC_REG_PCT_INT_CTRL,
0593             read_aux_reg(ARC_REG_PCT_INT_CTRL) | BIT(idx));
0594 
0595         event = pmu_cpu->act_counter[idx];
0596         hwc = &event->hw;
0597 
0598         WARN_ON_ONCE(hwc->idx != idx);
0599 
0600         arc_perf_event_update(event, &event->hw, event->hw.idx);
0601         perf_sample_data_init(&data, 0, hwc->last_period);
0602         if (arc_pmu_event_set_period(event)) {
0603             if (perf_event_overflow(event, &data, regs))
0604                 arc_pmu_stop(event, 0);
0605         }
0606 
0607         active_ints &= ~BIT(idx);
0608     } while (active_ints);
0609 
0610 done:
0611     arc_pmu_enable(&arc_pmu->pmu);
0612 
0613     return IRQ_HANDLED;
0614 }
0615 #else
0616 
0617 static irqreturn_t arc_pmu_intr(int irq, void *dev)
0618 {
0619     return IRQ_NONE;
0620 }
0621 
0622 #endif /* CONFIG_ISA_ARCV2 */
0623 
0624 static void arc_cpu_pmu_irq_init(void *data)
0625 {
0626     int irq = *(int *)data;
0627 
0628     enable_percpu_irq(irq, IRQ_TYPE_NONE);
0629 
0630     /* Clear all pending interrupt flags */
0631     write_aux_reg(ARC_REG_PCT_INT_ACT, 0xffffffff);
0632 }
0633 
0634 /* Event field occupies the bottom 15 bits of our config field */
0635 PMU_FORMAT_ATTR(event, "config:0-14");
0636 static struct attribute *arc_pmu_format_attrs[] = {
0637     &format_attr_event.attr,
0638     NULL,
0639 };
0640 
0641 static struct attribute_group arc_pmu_format_attr_gr = {
0642     .name = "format",
0643     .attrs = arc_pmu_format_attrs,
0644 };
0645 
0646 static ssize_t arc_pmu_events_sysfs_show(struct device *dev,
0647                      struct device_attribute *attr,
0648                      char *page)
0649 {
0650     struct perf_pmu_events_attr *pmu_attr;
0651 
0652     pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
0653     return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
0654 }
0655 
0656 /*
0657  * We don't add attrs here as we don't have pre-defined list of perf events.
0658  * We will generate and add attrs dynamically in probe() after we read HW
0659  * configuration.
0660  */
0661 static struct attribute_group arc_pmu_events_attr_gr = {
0662     .name = "events",
0663 };
0664 
0665 static void arc_pmu_add_raw_event_attr(int j, char *str)
0666 {
0667     memmove(arc_pmu->raw_entry[j].name, str, ARCPMU_EVENT_NAME_LEN - 1);
0668     arc_pmu->attr[j].attr.attr.name = arc_pmu->raw_entry[j].name;
0669     arc_pmu->attr[j].attr.attr.mode = VERIFY_OCTAL_PERMISSIONS(0444);
0670     arc_pmu->attr[j].attr.show = arc_pmu_events_sysfs_show;
0671     arc_pmu->attr[j].id = j;
0672     arc_pmu->attrs[j] = &(arc_pmu->attr[j].attr.attr);
0673 }
0674 
0675 static int arc_pmu_raw_alloc(struct device *dev)
0676 {
0677     arc_pmu->attr = devm_kmalloc_array(dev, arc_pmu->n_events + 1,
0678         sizeof(*arc_pmu->attr), GFP_KERNEL | __GFP_ZERO);
0679     if (!arc_pmu->attr)
0680         return -ENOMEM;
0681 
0682     arc_pmu->attrs = devm_kmalloc_array(dev, arc_pmu->n_events + 1,
0683         sizeof(*arc_pmu->attrs), GFP_KERNEL | __GFP_ZERO);
0684     if (!arc_pmu->attrs)
0685         return -ENOMEM;
0686 
0687     arc_pmu->raw_entry = devm_kmalloc_array(dev, arc_pmu->n_events,
0688         sizeof(*arc_pmu->raw_entry), GFP_KERNEL | __GFP_ZERO);
0689     if (!arc_pmu->raw_entry)
0690         return -ENOMEM;
0691 
0692     return 0;
0693 }
0694 
0695 static inline bool event_in_hw_event_map(int i, char *name)
0696 {
0697     if (!arc_pmu_ev_hw_map[i])
0698         return false;
0699 
0700     if (!strlen(arc_pmu_ev_hw_map[i]))
0701         return false;
0702 
0703     if (strcmp(arc_pmu_ev_hw_map[i], name))
0704         return false;
0705 
0706     return true;
0707 }
0708 
0709 static void arc_pmu_map_hw_event(int j, char *str)
0710 {
0711     int i;
0712 
0713     /* See if HW condition has been mapped to a perf event_id */
0714     for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) {
0715         if (event_in_hw_event_map(i, str)) {
0716             pr_debug("mapping perf event %2d to h/w event \'%8s\' (idx %d)\n",
0717                  i, str, j);
0718             arc_pmu->ev_hw_idx[i] = j;
0719         }
0720     }
0721 }
0722 
0723 static int arc_pmu_device_probe(struct platform_device *pdev)
0724 {
0725     struct arc_reg_pct_build pct_bcr;
0726     struct arc_reg_cc_build cc_bcr;
0727     int i, has_interrupts, irq = -1;
0728     int counter_size;   /* in bits */
0729 
0730     union cc_name {
0731         struct {
0732             u32 word0, word1;
0733             char sentinel;
0734         } indiv;
0735         char str[ARCPMU_EVENT_NAME_LEN];
0736     } cc_name;
0737 
0738 
0739     READ_BCR(ARC_REG_PCT_BUILD, pct_bcr);
0740     if (!pct_bcr.v) {
0741         pr_err("This core does not have performance counters!\n");
0742         return -ENODEV;
0743     }
0744     BUILD_BUG_ON(ARC_PERF_MAX_COUNTERS > 32);
0745     if (WARN_ON(pct_bcr.c > ARC_PERF_MAX_COUNTERS))
0746         return -EINVAL;
0747 
0748     READ_BCR(ARC_REG_CC_BUILD, cc_bcr);
0749     if (WARN(!cc_bcr.v, "Counters exist but No countable conditions?"))
0750         return -EINVAL;
0751 
0752     arc_pmu = devm_kzalloc(&pdev->dev, sizeof(struct arc_pmu), GFP_KERNEL);
0753     if (!arc_pmu)
0754         return -ENOMEM;
0755 
0756     arc_pmu->n_events = cc_bcr.c;
0757 
0758     if (arc_pmu_raw_alloc(&pdev->dev))
0759         return -ENOMEM;
0760 
0761     has_interrupts = is_isa_arcv2() ? pct_bcr.i : 0;
0762 
0763     arc_pmu->n_counters = pct_bcr.c;
0764     counter_size = 32 + (pct_bcr.s << 4);
0765 
0766     arc_pmu->max_period = (1ULL << counter_size) / 2 - 1ULL;
0767 
0768     pr_info("ARC perf\t: %d counters (%d bits), %d conditions%s\n",
0769         arc_pmu->n_counters, counter_size, cc_bcr.c,
0770         has_interrupts ? ", [overflow IRQ support]" : "");
0771 
0772     cc_name.str[ARCPMU_EVENT_NAME_LEN - 1] = 0;
0773     for (i = 0; i < PERF_COUNT_ARC_HW_MAX; i++)
0774         arc_pmu->ev_hw_idx[i] = -1;
0775 
0776     /* loop thru all available h/w condition indexes */
0777     for (i = 0; i < cc_bcr.c; i++) {
0778         write_aux_reg(ARC_REG_CC_INDEX, i);
0779         cc_name.indiv.word0 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME0));
0780         cc_name.indiv.word1 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME1));
0781 
0782         arc_pmu_map_hw_event(i, cc_name.str);
0783         arc_pmu_add_raw_event_attr(i, cc_name.str);
0784     }
0785 
0786     arc_pmu_events_attr_gr.attrs = arc_pmu->attrs;
0787     arc_pmu->attr_groups[ARCPMU_ATTR_GR_EVENTS] = &arc_pmu_events_attr_gr;
0788     arc_pmu->attr_groups[ARCPMU_ATTR_GR_FORMATS] = &arc_pmu_format_attr_gr;
0789 
0790     arc_pmu->pmu = (struct pmu) {
0791         .pmu_enable = arc_pmu_enable,
0792         .pmu_disable    = arc_pmu_disable,
0793         .event_init = arc_pmu_event_init,
0794         .add        = arc_pmu_add,
0795         .del        = arc_pmu_del,
0796         .start      = arc_pmu_start,
0797         .stop       = arc_pmu_stop,
0798         .read       = arc_pmu_read,
0799         .attr_groups    = arc_pmu->attr_groups,
0800     };
0801 
0802     if (has_interrupts) {
0803         irq = platform_get_irq(pdev, 0);
0804         if (irq >= 0) {
0805             int ret;
0806 
0807             arc_pmu->irq = irq;
0808 
0809             /* intc map function ensures irq_set_percpu_devid() called */
0810             ret = request_percpu_irq(irq, arc_pmu_intr, "ARC perf counters",
0811                          this_cpu_ptr(&arc_pmu_cpu));
0812 
0813             if (!ret)
0814                 on_each_cpu(arc_cpu_pmu_irq_init, &irq, 1);
0815             else
0816                 irq = -1;
0817         }
0818 
0819     }
0820 
0821     if (irq == -1)
0822         arc_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
0823 
0824     /*
0825      * perf parser doesn't really like '-' symbol in events name, so let's
0826      * use '_' in arc pct name as it goes to kernel PMU event prefix.
0827      */
0828     return perf_pmu_register(&arc_pmu->pmu, "arc_pct", PERF_TYPE_RAW);
0829 }
0830 
0831 static const struct of_device_id arc_pmu_match[] = {
0832     { .compatible = "snps,arc700-pct" },
0833     { .compatible = "snps,archs-pct" },
0834     {},
0835 };
0836 MODULE_DEVICE_TABLE(of, arc_pmu_match);
0837 
0838 static struct platform_driver arc_pmu_driver = {
0839     .driver = {
0840         .name       = "arc-pct",
0841         .of_match_table = of_match_ptr(arc_pmu_match),
0842     },
0843     .probe      = arc_pmu_device_probe,
0844 };
0845 
0846 module_platform_driver(arc_pmu_driver);
0847 
0848 MODULE_LICENSE("GPL");
0849 MODULE_AUTHOR("Mischa Jonker <mjonker@synopsys.com>");
0850 MODULE_DESCRIPTION("ARC PMU driver");
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