arc/kernel/intc-arcv2.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2014 Synopsys, Inc. (www.synopsys.com)
0004  */
0005
0006 #include <linux/interrupt.h>
0007 #include <linux/module.h>
0008 #include <linux/of.h>
0009 #include <linux/irqdomain.h>
0010 #include <linux/irqchip.h>
0011 #include <asm/irq.h>
0012
0013 #define NR_EXCEPTIONS   16
0014
0015 struct bcr_irq_arcv2 {
0016 #ifdef CONFIG_CPU_BIG_ENDIAN
0017     unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
0018 #else
0019     unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
0020 #endif
0021 };
0022
0023 /*
0024  * Early Hardware specific Interrupt setup
0025  * -Called very early (start_kernel -> setup_arch -> setup_processor)
0026  * -Platform Independent (must for any ARC Core)
0027  * -Needed for each CPU (hence not foldable into init_IRQ)
0028  */
0029 void arc_init_IRQ(void)
0030 {
0031     unsigned int tmp, irq_prio, i;
0032     struct bcr_irq_arcv2 irq_bcr;
0033
0034     struct aux_irq_ctrl {
0035 #ifdef CONFIG_CPU_BIG_ENDIAN
0036         unsigned int res3:18, save_idx_regs:1, res2:1,
0037                  save_u_to_u:1, save_lp_regs:1, save_blink:1,
0038                  res:4, save_nr_gpr_pairs:5;
0039 #else
0040         unsigned int save_nr_gpr_pairs:5, res:4,
0041                  save_blink:1, save_lp_regs:1, save_u_to_u:1,
0042                  res2:1, save_idx_regs:1, res3:18;
0043 #endif
0044     } ictrl;
0045
0046     *(unsigned int *)&ictrl = 0;
0047
0048 #ifndef CONFIG_ARC_IRQ_NO_AUTOSAVE
0049     ictrl.save_nr_gpr_pairs = 6;    /* r0 to r11 (r12 saved manually) */
0050     ictrl.save_blink = 1;
0051     ictrl.save_lp_regs = 1;     /* LP_COUNT, LP_START, LP_END */
0052     ictrl.save_u_to_u = 0;      /* user ctxt saved on kernel stack */
0053     ictrl.save_idx_regs = 1;    /* JLI, LDI, EI */
0054 #endif
0055
0056     WRITE_AUX(AUX_IRQ_CTRL, ictrl);
0057
0058     /*
0059      * ARCv2 core intc provides multiple interrupt priorities (upto 16).
0060      * Typical builds though have only two levels (0-high, 1-low)
0061      * Linux by default uses lower prio 1 for most irqs, reserving 0 for
0062      * NMI style interrupts in future (say perf)
0063      */
0064
0065     READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
0066
0067     irq_prio = irq_bcr.prio;    /* Encoded as N-1 for N levels */
0068     pr_info("archs-intc\t: %d priority levels (default %d)%s\n",
0069         irq_prio + 1, ARCV2_IRQ_DEF_PRIO,
0070         irq_bcr.firq ? " FIRQ (not used)":"");
0071
0072     /*
0073      * Set a default priority for all available interrupts to prevent
0074      * switching of register banks if Fast IRQ and multiple register banks
0075      * are supported by CPU.
0076      * Also disable private-per-core IRQ lines so faulty external HW won't
0077      * trigger interrupt that kernel is not ready to handle.
0078      */
0079     for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
0080         write_aux_reg(AUX_IRQ_SELECT, i);
0081         write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
0082
0083         /*
0084          * Only mask cpu private IRQs here.
0085          * "common" interrupts are masked at IDU, otherwise it would
0086          * need to be unmasked at each cpu, with IPIs
0087          */
0088         if (i < FIRST_EXT_IRQ)
0089             write_aux_reg(AUX_IRQ_ENABLE, 0);
0090     }
0091
0092     /* setup status32, don't enable intr yet as kernel doesn't want */
0093     tmp = read_aux_reg(ARC_REG_STATUS32);
0094     tmp |= ARCV2_IRQ_DEF_PRIO << 1;
0095     tmp &= ~STATUS_IE_MASK;
0096     asm volatile("kflag %0  \n"::"r"(tmp));
0097 }
0098
0099 static void arcv2_irq_mask(struct irq_data *data)
0100 {
0101     write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
0102     write_aux_reg(AUX_IRQ_ENABLE, 0);
0103 }
0104
0105 static void arcv2_irq_unmask(struct irq_data *data)
0106 {
0107     write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
0108     write_aux_reg(AUX_IRQ_ENABLE, 1);
0109 }
0110
0111 void arcv2_irq_enable(struct irq_data *data)
0112 {
0113     /* set default priority */
0114     write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
0115     write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
0116
0117     /*
0118      * hw auto enables (linux unmask) all by default
0119      * So no need to do IRQ_ENABLE here
0120      * XXX: However OSCI LAN need it
0121      */
0122     write_aux_reg(AUX_IRQ_ENABLE, 1);
0123 }
0124
0125 static struct irq_chip arcv2_irq_chip = {
0126     .name           = "ARCv2 core Intc",
0127     .irq_mask   = arcv2_irq_mask,
0128     .irq_unmask = arcv2_irq_unmask,
0129     .irq_enable = arcv2_irq_enable
0130 };
0131
0132 static int arcv2_irq_map(struct irq_domain *d, unsigned int irq,
0133              irq_hw_number_t hw)
0134 {
0135     /*
0136      * core intc IRQs [16, 23]:
0137      * Statically assigned always private-per-core (Timers, WDT, IPI, PCT)
0138      */
0139     if (hw < FIRST_EXT_IRQ) {
0140         /*
0141          * A subsequent request_percpu_irq() fails if percpu_devid is
0142          * not set. That in turns sets NOAUTOEN, meaning each core needs
0143          * to call enable_percpu_irq()
0144          */
0145         irq_set_percpu_devid(irq);
0146         irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_percpu_irq);
0147     } else {
0148         irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_level_irq);
0149     }
0150
0151     return 0;
0152 }
0153
0154 static const struct irq_domain_ops arcv2_irq_ops = {
0155     .xlate = irq_domain_xlate_onecell,
0156     .map = arcv2_irq_map,
0157 };
0158
0159
0160 static int __init
0161 init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
0162 {
0163     struct irq_domain *root_domain;
0164     struct bcr_irq_arcv2 irq_bcr;
0165     unsigned int nr_cpu_irqs;
0166
0167     READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
0168     nr_cpu_irqs = irq_bcr.irqs + NR_EXCEPTIONS;
0169
0170     if (parent)
0171         panic("DeviceTree incore intc not a root irq controller\n");
0172
0173     root_domain = irq_domain_add_linear(intc, nr_cpu_irqs, &arcv2_irq_ops, NULL);
0174     if (!root_domain)
0175         panic("root irq domain not avail\n");
0176
0177     /*
0178      * Needed for primary domain lookup to succeed
0179      * This is a primary irqchip, and can never have a parent
0180      */
0181     irq_set_default_host(root_domain);
0182
0183 #ifdef CONFIG_SMP
0184     irq_create_mapping(root_domain, IPI_IRQ);
0185 #endif
0186     irq_create_mapping(root_domain, SOFTIRQ_IRQ);
0187
0188     return 0;
0189 }
0190
0191 IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ);