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0008 #include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
0009 #include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */
0010 #include <asm/errno.h>
0011 #include <asm/arcregs.h>
0012 #include <asm/irqflags.h>
0013 #include <asm/mmu.h>
0014
0015 ; A maximum number of supported interrupts in the core interrupt controller.
0016 ; This number is not equal to the maximum interrupt number (256) because
0017 ; first 16 lines are reserved for exceptions and are not configurable.
0018 #define NR_CPU_IRQS 240
0019
0020 .cpu HS
0021
0022 #define VECTOR .word
0023
0024 ;############################ Vector Table #################################
0025
0026 .section .vector,"a",@progbits
0027 .align 4
0028
0029 # Initial 16 slots are Exception Vectors
0030 VECTOR res_service ; Reset Vector
0031 VECTOR mem_service ; Mem exception
0032 VECTOR instr_service ; Instrn Error
0033 VECTOR EV_MachineCheck ; Fatal Machine check
0034 VECTOR EV_TLBMissI ; Intruction TLB miss
0035 VECTOR EV_TLBMissD ; Data TLB miss
0036 VECTOR EV_TLBProtV ; Protection Violation
0037 VECTOR EV_PrivilegeV ; Privilege Violation
0038 VECTOR EV_SWI ; Software Breakpoint
0039 VECTOR EV_Trap ; Trap exception
0040 VECTOR EV_Extension ; Extn Instruction Exception
0041 VECTOR EV_DivZero ; Divide by Zero
0042 VECTOR EV_DCError ; Data Cache Error
0043 VECTOR EV_Misaligned ; Misaligned Data Access
0044 VECTOR reserved ; Reserved slots
0045 VECTOR reserved ; Reserved slots
0046
0047 # Begin Interrupt Vectors
0048 VECTOR handle_interrupt ; (16) Timer0
0049 VECTOR handle_interrupt ; unused (Timer1)
0050 VECTOR handle_interrupt ; unused (WDT)
0051 VECTOR handle_interrupt ; (19) Inter core Interrupt (IPI)
0052 VECTOR handle_interrupt ; (20) perf Interrupt
0053 VECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI)
0054 VECTOR handle_interrupt ; unused
0055 VECTOR handle_interrupt ; (23) unused
0056 # End of fixed IRQs
0057
0058 .rept NR_CPU_IRQS - 8
0059 VECTOR handle_interrupt
0060 .endr
0061
0062 .section .text, "ax",@progbits
0063
0064 reserved:
0065 flag 1 ; Unexpected event, halt
0066
0067 ;##################### Interrupt Handling ##############################
0068
0069 ENTRY(handle_interrupt)
0070
0071 INTERRUPT_PROLOGUE
0072
0073 # irq control APIs local_irq_save/restore/disable/enable fiddle with
0074 # global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio)
0075 # However a taken interrupt doesn't clear these bits. Thus irqs_disabled()
0076 # query in hard ISR path would return false (since .IE is set) which would
0077 # trips genirq interrupt handling asserts.
0078 #
0079 # So do a "soft" disable of interrutps here.
0080 #
0081 # Note this disable is only for consistent book-keeping as further interrupts
0082 # will be disabled anyways even w/o this. Hardware tracks active interrupts
0083 # seperately in AUX_IRQ_ACT.active and will not take new interrupts
0084 # unless this one returns (or higher prio becomes pending in 2-prio scheme)
0085
0086 IRQ_DISABLE
0087
0088 ; icause is banked: one per priority level
0089 ; so a higher prio interrupt taken here won't clobber prev prio icause
0090 lr r0, [ICAUSE]
0091 mov blink, ret_from_exception
0092
0093 b.d arch_do_IRQ
0094 mov r1, sp
0095
0096 END(handle_interrupt)
0097
0098 ;################### Non TLB Exception Handling #############################
0099
0100 ENTRY(EV_SWI)
0101 ; TODO: implement this
0102 EXCEPTION_PROLOGUE
0103 b ret_from_exception
0104 END(EV_SWI)
0105
0106 ENTRY(EV_DivZero)
0107 ; TODO: implement this
0108 EXCEPTION_PROLOGUE
0109 b ret_from_exception
0110 END(EV_DivZero)
0111
0112 ENTRY(EV_DCError)
0113 ; TODO: implement this
0114 EXCEPTION_PROLOGUE
0115 b ret_from_exception
0116 END(EV_DCError)
0117
0118 ; ---------------------------------------------
0119 ; Memory Error Exception Handler
0120 ; - Unlike ARCompact, handles Bus errors for both User/Kernel mode,
0121 ; Instruction fetch or Data access, under a single Exception Vector
0122 ; ---------------------------------------------
0123
0124 ENTRY(mem_service)
0125
0126 EXCEPTION_PROLOGUE
0127
0128 lr r0, [efa]
0129 mov r1, sp
0130
0131 FAKE_RET_FROM_EXCPN
0132
0133 bl do_memory_error
0134 b ret_from_exception
0135 END(mem_service)
0136
0137 ENTRY(EV_Misaligned)
0138
0139 EXCEPTION_PROLOGUE
0140
0141 lr r0, [efa] ; Faulting Data address
0142 mov r1, sp
0143
0144 FAKE_RET_FROM_EXCPN
0145
0146 SAVE_CALLEE_SAVED_USER
0147 mov r2, sp ; callee_regs
0148
0149 bl do_misaligned_access
0150
0151 ; TBD: optimize - do this only if a callee reg was involved
0152 ; either a dst of emulated LD/ST or src with address-writeback
0153 RESTORE_CALLEE_SAVED_USER
0154
0155 b ret_from_exception
0156 END(EV_Misaligned)
0157
0158 ; ---------------------------------------------
0159 ; Protection Violation Exception Handler
0160 ; ---------------------------------------------
0161
0162 ENTRY(EV_TLBProtV)
0163
0164 EXCEPTION_PROLOGUE
0165
0166 lr r0, [efa] ; Faulting Data address
0167 mov r1, sp ; pt_regs
0168
0169 FAKE_RET_FROM_EXCPN
0170
0171 mov blink, ret_from_exception
0172 b do_page_fault
0173
0174 END(EV_TLBProtV)
0175
0176 ; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they
0177 ; need to call do_page_fault().
0178 ; ECR in pt_regs provides whether access was R/W/X
0179
0180 .global call_do_page_fault
0181 .set call_do_page_fault, EV_TLBProtV
0182
0183 ;############# Common Handlers for ARCompact and ARCv2 ##############
0184
0185 #include "entry.S"
0186
0187 ;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ##############
0188 ;
0189 ; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
0190 ; IRQ shd definitely not happen between now and rtie
0191 ; All 2 entry points to here already disable interrupts
0192
0193 .Lrestore_regs:
0194 restore_regs:
0195
0196 # Interrpts are actually disabled from this point on, but will get
0197 # reenabled after we return from interrupt/exception.
0198 # But irq tracer needs to be told now...
0199 TRACE_ASM_IRQ_ENABLE
0200
0201 ld r0, [sp, PT_status32] ; U/K mode at time of entry
0202 lr r10, [AUX_IRQ_ACT]
0203
0204 bmsk r11, r10, 15 ; extract AUX_IRQ_ACT.active
0205 breq r11, 0, .Lexcept_ret ; No intr active, ret from Exception
0206
0207 ;####### Return from Intr #######
0208
0209 .Lisr_ret:
0210
0211 debug_marker_l1:
0212 ; bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot
0213 btst r0, STATUS_DE_BIT ; Z flag set if bit clear
0214 bnz .Lintr_ret_to_delay_slot ; branch if STATUS_DE_BIT set
0215
0216 ; Handle special case #1: (Entry via Exception, Return via IRQ)
0217 ;
0218 ; Exception in U mode, preempted in kernel, Intr taken (K mode), orig
0219 ; task now returning to U mode (riding the Intr)
0220 ; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP
0221 ; won't be switched to correct U mode value (from AUX_SP)
0222 ; So force AUX_IRQ_ACT.U for such a case
0223
0224 btst r0, STATUS_U_BIT ; Z flag set if K (Z clear for U)
0225 bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U
0226 sr r11, [AUX_IRQ_ACT]
0227
0228 INTERRUPT_EPILOGUE
0229 rtie
0230
0231 ;####### Return from Exception / pure kernel mode #######
0232
0233 .Lexcept_ret: ; Expects r0 has PT_status32
0234
0235 debug_marker_syscall:
0236 EXCEPTION_EPILOGUE
0237 rtie
0238
0239 ;####### Return from Intr to insn in delay slot #######
0240
0241 ; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ)
0242 ;
0243 ; Intr returning to a Delay Slot (DS) insn
0244 ; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
0245 ; entry was via Exception in DS which got preempted in kernel).
0246 ;
0247 ; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround
0248 ;
0249 ; Solution is to drop out of interrupt context into pure kernel mode
0250 ; and return from pure kernel mode which does right things for delay slot
0251
0252 .Lintr_ret_to_delay_slot:
0253 debug_marker_ds:
0254
0255 ld r2, [@intr_to_DE_cnt]
0256 add r2, r2, 1
0257 st r2, [@intr_to_DE_cnt]
0258
0259 ; drop out of interrupt context (clear AUX_IRQ_ACT.active)
0260 bmskn r11, r10, 15
0261 sr r11, [AUX_IRQ_ACT]
0262 b .Lexcept_ret
0263
0264 END(ret_from_exception)
