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0009 #ifndef __ASM_PERF_EVENT_H
0010 #define __ASM_PERF_EVENT_H
0011
0012
0013 #define ARC_PERF_MAX_COUNTERS 32
0014
0015 #define ARC_REG_CC_BUILD 0xF6
0016 #define ARC_REG_CC_INDEX 0x240
0017 #define ARC_REG_CC_NAME0 0x241
0018 #define ARC_REG_CC_NAME1 0x242
0019
0020 #define ARC_REG_PCT_BUILD 0xF5
0021 #define ARC_REG_PCT_COUNTL 0x250
0022 #define ARC_REG_PCT_COUNTH 0x251
0023 #define ARC_REG_PCT_SNAPL 0x252
0024 #define ARC_REG_PCT_SNAPH 0x253
0025 #define ARC_REG_PCT_CONFIG 0x254
0026 #define ARC_REG_PCT_CONTROL 0x255
0027 #define ARC_REG_PCT_INDEX 0x256
0028 #define ARC_REG_PCT_INT_CNTL 0x25C
0029 #define ARC_REG_PCT_INT_CNTH 0x25D
0030 #define ARC_REG_PCT_INT_CTRL 0x25E
0031 #define ARC_REG_PCT_INT_ACT 0x25F
0032
0033 #define ARC_REG_PCT_CONFIG_USER (1 << 18)
0034 #define ARC_REG_PCT_CONFIG_KERN (1 << 19)
0035
0036 #define ARC_REG_PCT_CONTROL_CC (1 << 16)
0037 #define ARC_REG_PCT_CONTROL_SN (1 << 17)
0038
0039 struct arc_reg_pct_build {
0040 #ifdef CONFIG_CPU_BIG_ENDIAN
0041 unsigned int m:8, c:8, r:5, i:1, s:2, v:8;
0042 #else
0043 unsigned int v:8, s:2, i:1, r:5, c:8, m:8;
0044 #endif
0045 };
0046
0047 struct arc_reg_cc_build {
0048 #ifdef CONFIG_CPU_BIG_ENDIAN
0049 unsigned int c:16, r:8, v:8;
0050 #else
0051 unsigned int v:8, r:8, c:16;
0052 #endif
0053 };
0054
0055 #define PERF_COUNT_ARC_DCLM (PERF_COUNT_HW_MAX + 0)
0056 #define PERF_COUNT_ARC_DCSM (PERF_COUNT_HW_MAX + 1)
0057 #define PERF_COUNT_ARC_ICM (PERF_COUNT_HW_MAX + 2)
0058 #define PERF_COUNT_ARC_BPOK (PERF_COUNT_HW_MAX + 3)
0059 #define PERF_COUNT_ARC_EDTLB (PERF_COUNT_HW_MAX + 4)
0060 #define PERF_COUNT_ARC_EITLB (PERF_COUNT_HW_MAX + 5)
0061 #define PERF_COUNT_ARC_LDC (PERF_COUNT_HW_MAX + 6)
0062 #define PERF_COUNT_ARC_STC (PERF_COUNT_HW_MAX + 7)
0063
0064 #define PERF_COUNT_ARC_HW_MAX (PERF_COUNT_HW_MAX + 8)
0065
0066 #ifdef CONFIG_PERF_EVENTS
0067 #define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs
0068 #endif
0069
0070 #endif