include/asm/mmu_context.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
0004  *
0005  * vineetg: May 2011
0006  *  -Refactored get_new_mmu_context( ) to only handle live-mm.
0007  *   retiring-mm handled in other hooks
0008  *
0009  * Vineetg: March 25th, 2008: Bug #92690
0010  *  -Major rewrite of Core ASID allocation routine get_new_mmu_context
0011  *
0012  * Amit Bhor, Sameer Dhavale: Codito Technologies 2004
0013  */
0014
0015 #ifndef _ASM_ARC_MMU_CONTEXT_H
0016 #define _ASM_ARC_MMU_CONTEXT_H
0017
0018 #include <linux/sched/mm.h>
0019
0020 #include <asm/tlb.h>
0021 #include <asm-generic/mm_hooks.h>
0022
0023 /*      ARC ASID Management
0024  *
0025  * MMU tags TLBs with an 8-bit ASID, avoiding need to flush the TLB on
0026  * context-switch.
0027  *
0028  * ASID is managed per cpu, so task threads across CPUs can have different
0029  * ASID. Global ASID management is needed if hardware supports TLB shootdown
0030  * and/or shared TLB across cores, which ARC doesn't.
0031  *
0032  * Each task is assigned unique ASID, with a simple round-robin allocator
0033  * tracked in @asid_cpu. When 8-bit value rolls over,a new cycle is started
0034  * over from 0, and TLB is flushed
0035  *
0036  * A new allocation cycle, post rollover, could potentially reassign an ASID
0037  * to a different task. Thus the rule is to refresh the ASID in a new cycle.
0038  * The 32 bit @asid_cpu (and mm->asid) have 8 bits MMU PID and rest 24 bits
0039  * serve as cycle/generation indicator and natural 32 bit unsigned math
0040  * automagically increments the generation when lower 8 bits rollover.
0041  */
0042
0043 #define MM_CTXT_ASID_MASK   0x000000ff /* MMU PID reg :8 bit PID */
0044 #define MM_CTXT_CYCLE_MASK  (~MM_CTXT_ASID_MASK)
0045
0046 #define MM_CTXT_FIRST_CYCLE (MM_CTXT_ASID_MASK + 1)
0047 #define MM_CTXT_NO_ASID     0UL
0048
0049 #define asid_mm(mm, cpu)    mm->context.asid[cpu]
0050 #define hw_pid(mm, cpu)     (asid_mm(mm, cpu) & MM_CTXT_ASID_MASK)
0051
0052 DECLARE_PER_CPU(unsigned int, asid_cache);
0053 #define asid_cpu(cpu)       per_cpu(asid_cache, cpu)
0054
0055 /*
0056  * Get a new ASID if task doesn't have a valid one (unalloc or from prev cycle)
0057  * Also set the MMU PID register to existing/updated ASID
0058  */
0059 static inline void get_new_mmu_context(struct mm_struct *mm)
0060 {
0061     const unsigned int cpu = smp_processor_id();
0062     unsigned long flags;
0063
0064     local_irq_save(flags);
0065
0066     /*
0067      * Move to new ASID if it was not from current alloc-cycle/generation.
0068      * This is done by ensuring that the generation bits in both mm->ASID
0069      * and cpu's ASID counter are exactly same.
0070      *
0071      * Note: Callers needing new ASID unconditionally, independent of
0072      *   generation, e.g. local_flush_tlb_mm() for forking  parent,
0073      *   first need to destroy the context, setting it to invalid
0074      *   value.
0075      */
0076     if (!((asid_mm(mm, cpu) ^ asid_cpu(cpu)) & MM_CTXT_CYCLE_MASK))
0077         goto set_hw;
0078
0079     /* move to new ASID and handle rollover */
0080     if (unlikely(!(++asid_cpu(cpu) & MM_CTXT_ASID_MASK))) {
0081
0082         local_flush_tlb_all();
0083
0084         /*
0085          * Above check for rollover of 8 bit ASID in 32 bit container.
0086          * If the container itself wrapped around, set it to a non zero
0087          * "generation" to distinguish from no context
0088          */
0089         if (!asid_cpu(cpu))
0090             asid_cpu(cpu) = MM_CTXT_FIRST_CYCLE;
0091     }
0092
0093     /* Assign new ASID to tsk */
0094     asid_mm(mm, cpu) = asid_cpu(cpu);
0095
0096 set_hw:
0097     mmu_setup_asid(mm, hw_pid(mm, cpu));
0098
0099     local_irq_restore(flags);
0100 }
0101
0102 /*
0103  * Initialize the context related info for a new mm_struct
0104  * instance.
0105  */
0106 #define init_new_context init_new_context
0107 static inline int
0108 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
0109 {
0110     int i;
0111
0112     for_each_possible_cpu(i)
0113         asid_mm(mm, i) = MM_CTXT_NO_ASID;
0114
0115     return 0;
0116 }
0117
0118 #define destroy_context destroy_context
0119 static inline void destroy_context(struct mm_struct *mm)
0120 {
0121     unsigned long flags;
0122
0123     /* Needed to elide CONFIG_DEBUG_PREEMPT warning */
0124     local_irq_save(flags);
0125     asid_mm(mm, smp_processor_id()) = MM_CTXT_NO_ASID;
0126     local_irq_restore(flags);
0127 }
0128
0129 /* Prepare the MMU for task: setup PID reg with allocated ASID
0130     If task doesn't have an ASID (never alloc or stolen, get a new ASID)
0131 */
0132 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
0133                  struct task_struct *tsk)
0134 {
0135     const int cpu = smp_processor_id();
0136
0137     /*
0138      * Note that the mm_cpumask is "aggregating" only, we don't clear it
0139      * for the switched-out task, unlike some other arches.
0140      * It is used to enlist cpus for sending TLB flush IPIs and not sending
0141      * it to CPUs where a task once ran-on, could cause stale TLB entry
0142      * re-use, specially for a multi-threaded task.
0143      * e.g. T1 runs on C1, migrates to C3. T2 running on C2 munmaps.
0144      *      For a non-aggregating mm_cpumask, IPI not sent C1, and if T1
0145      *      were to re-migrate to C1, it could access the unmapped region
0146      *      via any existing stale TLB entries.
0147      */
0148     cpumask_set_cpu(cpu, mm_cpumask(next));
0149
0150     mmu_setup_pgd(next, next->pgd);
0151
0152     get_new_mmu_context(next);
0153 }
0154
0155 /*
0156  * activate_mm defaults (in asm-generic) to switch_mm and is called at the
0157  * time of execve() to get a new ASID Note the subtlety here:
0158  * get_new_mmu_context() behaves differently here vs. in switch_mm(). Here
0159  * it always returns a new ASID, because mm has an unallocated "initial"
0160  * value, while in latter, it moves to a new ASID, only if it was
0161  * unallocated
0162  */
0163
0164 /* it seemed that deactivate_mm( ) is a reasonable place to do book-keeping
0165  * for retiring-mm. However destroy_context( ) still needs to do that because
0166  * between mm_release( ) = >deactive_mm( ) and
0167  * mmput => .. => __mmdrop( ) => destroy_context( )
0168  * there is a good chance that task gets sched-out/in, making it's ASID valid
0169  * again (this teased me for a whole day).
0170  */
0171
0172 #include <asm-generic/mmu_context.h>
0173
0174 #endif /* __ASM_ARC_MMU_CONTEXT_H */